u-boot.git/cpu/mpc85xx, branch v2009.01-rc1

Update U-Boot's build timestamp on every compile

2008-12-06T22:36:43Z

Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser

85xx: init gd as early as possible

2008-12-04T09:15:43Z

Moved up the initialization of GD so C code like set_tlb() can use gd->flags to determine if we've relocated or not in the future. Signed-off-by: Kumar Gala Acked-by: Andy Fleming

85xx: Fix relocation of CCSRBAR

2008-12-04T09:15:43Z

If the virtual address for CCSRBAR is the same after relocation but the physical address is changing we'd end up having two TLB entries with the same VA. Instead we new us the new CCSRBAR virt address + 4k as a temp virt address to access the old CCSRBAR to relocate it. Signed-off-by: Kumar Gala Acked-by: Andy Fleming

85xx: Add PORDEVSR_PCI1 define

2008-12-04T09:15:43Z

Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser Signed-off-by: Andy Fleming

85xx: Add CPU 2 errata workaround to all 8548 boards

2008-12-04T04:46:42Z

All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser Acked-by: Andy Fleming

Moved initialization of QE Ethernet controller to cpu_eth_init()

2008-11-10T05:38:03Z

Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren

Moved initialization of FCC Ethernet controller to cpu_eth_init

2008-11-10T05:38:02Z

Affected boards: Several MPC8xx boards Several MPC8260/MPC8272 boards Several MPC85xx boards Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren

Fix typo in cpu/mpc85xx/cpu.c

2008-11-10T05:38:02Z

CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC Signed-off-by: Ben Warren

85xx: Fix the incorrect register used for DDR erratum1

2008-10-24T22:29:37Z

The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu

85xx: Add basic e500mc core support

2008-10-24T20:10:47Z

Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala