u-boot.git/cpu/mpc85xx, branch v2009.03 Unnamed repository; edit this file 'description' to name the repository. Fix mpc85xx ddr-gen3 ddr_sdram_cfg. 2009-03-09T22:46:09+00:00 Ed Swarthout Ed.Swarthout@freescale.com 2009-02-24T08:37:59+00:00 0ee84b88b78bce425190d8cd7adf4c30cba0c2f0 Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> 
Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Coding style cleanup, update CHANGELOG 2009-02-18T23:41:08+00:00 Wolfgang Denk wd@denx.de 2009-02-18T23:41:08+00:00 1bba30efe1717bea13026e15c7c7d906419fac69 Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
85xx: Add eSDHC support for 8536 DS 2009-02-17T00:07:43+00:00 Andy Fleming afleming@freescale.com 2008-10-30T21:51:33+00:00 80522dc8369a89938369fbcee572e662373bc9a3 Signed-off-by: Andy Fleming <afleming@freescale.com> 
Signed-off-by: Andy Fleming <afleming@freescale.com>
32bit BUg fix for DDR2 on 8572 2009-02-17T00:06:03+00:00 Poonam_Aggrwal-b10812 b10812@freescale.com 2009-01-04T03:16:38+00:00 e1be0d25ecf494ae81245ca438738ba839d6329b This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net> 
This errata fix is required for 32 bit DDR2 controller on 8572.
May  also be required for P10XX20XX platforms

Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
mpc85xx: Add support for the P2020 2009-02-17T00:05:55+00:00 Srikanth Srinivasan srikanth.srinivasan@freescale.com 2009-01-21T23:17:33+00:00 8d949aff38cfb4388cbd73876e77bcd06d601f20 Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
85xx: Fix how we map DDR memory 2009-02-17T00:05:51+00:00 Kumar Gala galak@kernel.crashing.org 2009-02-06T15:56:35+00:00 f8523cb0815b2d3d2d780b7d49ca614105555f58 Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
85xx: Format cpu freq printing to handle 8 cores 2009-02-17T00:05:50+00:00 Kumar Gala galak@kernel.crashing.org 2009-02-04T15:35:57+00:00 b29dee3c906e9daaf6baf7772d2e15e26b8636b8 Only print 4 cpu freq per line. This way when we have 8 cores its a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Only print 4 cpu freq per line.  This way when we have 8 cores its a
bit more readable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add secondary CPUs processor frequency for e500 core 2009-01-23T23:03:14+00:00 Haiying Wang Haiying.Wang@freescale.com 2009-01-15T16:58:35+00:00 2fc7eb0cfc608c9369001d57a0411af5e6a58f7c This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> 
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards 2009-01-23T23:03:13+00:00 Kumar Gala galak@kernel.crashing.org 2008-12-02T22:08:37+00:00 5f91ef6acdbadec33e0192049e2b24a1d9692f1d Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards 2009-01-23T23:03:13+00:00 Kumar Gala galak@kernel.crashing.org 2008-12-02T22:08:36+00:00 10795f42cb94e71bcb262b615084f69dd886399a Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com> 
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>