u-boot.git/cpu/mpc85xx, branch v2009.11

ppc/85xx: Fix how we determine the number of CAM entries

2009-11-13T15:11:01+00:00

We were incorrectly use the max CAM size as the number of entries in
the array for setting up the addrmap.  We should be using the NENTRY
field which is the low 12-bits of TLB1CFG.

Signed-off-by: Kumar Gala

ppc/85xx: Fix misc L2 cache enabling bug

2009-10-31T15:59:52+00:00

We need loop-check the flash clear lock and enable bit for L2 cache.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

Coding Style cleanup; update CHANGELOG, prepare -rc1

2009-10-27T23:49:47+00:00

Signed-off-by: Wolfgang Denk

mpc85xx: Add eSDHC support for MPC8569E-MDS boards

2009-10-27T14:36:48+00:00

eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.

Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).

So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.

Signed-off-by: Anton Vorontsov 
Signed-off-by: Kumar Gala

85xx: MP Boot Page Translation update

2009-10-27T14:34:57+00:00

This change has 3 goals:
- Have secondary cores be released into spin loops at their 'true'
  address in SDRAM.  Previously, secondary cores were put into spin
  loops in the 0xfffffxxx address range which required that boot page
  translation was always enabled while cores were in their spin loops.

- Allow the TLB window that the primary core uses to access the
  secondary cores boot page to be placed at any address.  Previously, a
  TLB window at 0xfffff000 was always used to access the seconary cores'
  boot page.  This TLB address requirement overlapped with other
  peripherals on some boards (eg XPedite5370).  By default, the boot
  page TLB will still use the 0xfffffxxx address range, but this can be
  overridden on a board-by-board basis by defining a custom
  CONFIG_BPTR_VIRT_ADDR.  Note that the TLB used to map the boot page
  remains in use while U-Boot executes.  Previously it was only
  temporarily used, then restored to its initial value.

- Allow Boot Page Translation to be disabled on bootup.  Previously,
  Boot Page Translation was always left enabled after secondary cores
  were brought out of reset.  This caused the 0xfffffxxx address range
  to somewhat "magically" be translated to an address in SDRAM.  Some
  boards may not want this oddity in their memory map, so defining
  CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after
  the secondary cores are initialized.

These changes are only applicable to 85xx boards with CONFIG_MP defined.

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

ppc/85xx: Fix crashes due to generation of SPE instruction

2009-10-27T02:35:45+00:00

U-Boot crashed on the last instruction:

int parse_stream_outer(struct in_str *inp, int flag)
{
effa4784:       94 21 ff 38     stwu    r1,-200(r1)
effa4788:       7c 08 02 a6     mflr    r0
effa478c:       42 9f 00 05     bcl-    20,4*cr7+so,effa4790 
effa4790:       7d 80 00 26     mfcr    r12
effa4794:       13 c1 b3 21     evstdd  r30,176(r1)

...which is a  SPE instruction, although -mno-spe was used.

tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version
powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3

Seems to be a known issue (since 2008-04?!)

Googled some, turns out this patch/workaround works for me on MPC8536DS.

See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info

Signed-off-by: Leon Woestenberg 
Signed-off-by: Kumar Gala

ppc/85xx: Make L2 support more robust

2009-10-27T02:24:51+00:00

According the user manual, we need loop-check the L2 enable bit set.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

relocation: Do not relocate NULL pointers.

2009-10-08T07:33:36+00:00

NULL is an absolute value and should not be relocated.
After this correction code like:
 void weak_fun(void) __attribute__((weak));
 printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.

Signed-off-by: Joakim Tjernlund

85xx: Ensure BSS segment isn't linked at address 0

2009-10-07T22:33:47+00:00

When U-Boot is relocated from flash to RAM pointers are modified
accordingly.  However, pointers initialzed with NULL values should not
be modified so that they maintain their intended NULL value.  If the
BSS segment is linked at address 0 its address will not be
updated as necessary during relocation.

This is a temporary workaround.  The end goal is to add support to
U-Boot to dynamically locate the BSS at an arbitrary address at
runtime.  When the ability to fixup the BSS inteligently is
added, this workaround can be removed and the 85xx link script
can put the BSS at a fixed address at link time.

Signed-off-by: Peter Tyser

ppc: Enable full relocation to RAM

2009-10-03T08:15:45+00:00

The following changes allow U-Boot to fully relocate from flash to
RAM:
 - Remove linker scripts' .fixup sections from the .text section
 - Add -mrelocatable to PLATFORM_RELFLAGS for all boards
 - Define CONFIG_RELOC_FIXUP_WORKS for all boards

Previously, U-Boot would partially relocate, but statically initialized
pointers needed to be manually relocated.

Signed-off-by: Peter Tyser