u-boot.git/cpu/mpc86xx/cpu.c, branch master

ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU

2010-04-13T07:13:16+00:00

Signed-off-by: Peter Tyser

mpc86xx: set the DDR BATs after calculating true DDR size

2010-03-30T15:50:22+00:00

After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly.  This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.

On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way.  If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation.  The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).

Currently we are limited to power of two sized DDR since we only use a
single bat.  If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().

2009-09-08T14:10:08+00:00

While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

ppc/85xx,86xx: Handling Unknown SOC version

2009-09-08T14:10:08+00:00

Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx

2009-08-28T22:12:38+00:00

The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

8xxx: Refactored common cpu specific code for 85xx/86xx into one file.

2009-08-28T22:12:38+00:00

Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

8xxx: Break out DMA code to a common file

2009-07-02T04:01:51+00:00

DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

86xx: Add CPU_TYPE_ENTRY support

2009-06-30T13:24:22+00:00

Unify with 83xx and 85xx and use CPU_TYPE_ENTRY.  We are going to use
this to convey the # of cores and DDR width in the near future so its
good to keep in sync.

Signed-off-by: Kumar Gala

fsl/85xx, 86xx: Sync up DMA code

2009-06-12T22:17:58+00:00

The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala

fsl: Create common fsl_dma.h for 85xx and 86xx cpus

2009-06-12T22:17:45+00:00

Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication

Signed-off-by: Peter Tyser 
Signed-off-by: Kumar Gala