u-boot.git/cpu/mpc86xx, branch v2008.10

mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache

2008-10-13T11:57:14+00:00

This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.

lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.

Signed-off-by: Nick Spence

86xx: remove redudant code with lib_ppc/interrupts.c

2008-10-13T11:56:18+00:00

For some reason we duplicated the majority of code in lib_ppc/interrupts.c
Not know how that happened, but there is no good reason for it.

Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.

Signed-off-by: Kumar Gala

Pass in tsec_info struct through tsec_initialize

2008-09-03T04:18:15+00:00

The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming 
Signed-off-by: Ben Warren

FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.

2008-08-27T22:35:56+00:00

Signed-off-by: Kumar Gala

FSL DDR: Remove old SPD support from cpu/mpc86xx

2008-08-27T00:06:05+00:00

All 86xx boards have been converted to the new code so we can
remove the old SPD DDR setup code.

Signed-off-by: Kumar Gala

FSL DDR: Add 86xx specific register setting

2008-08-27T00:06:01+00:00

Signed-off-by: Kumar Gala

FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

2008-08-27T00:05:58+00:00

The main purpose of this rewrite it to be able to share the same
initialization code on all FSL PowerPC products that have DDR
controllers.  (83xx, 85xx, 86xx).

The code is broken up into the following steps:
	GET_SPD
	COMPUTE_DIMM_PARMS
	COMPUTE_COMMON_PARMS
	GATHER_OPTS
	ASSIGN_ADDRESSES
	COMPUTE_REGS
	PROGRAM_REGS

This allows us to share more code an easily allow for board specific code
overrides.

Additionally this code base adds support for >4G of DDR and provides a
foundation for supporting interleaving on processors with more than one
controller.

Signed-off-by: James Yang 
Signed-off-by: Jon Loeliger 
Signed-off-by: Becky Bruce 
Signed-off-by: Ed Swarthout 
Signed-off-by: Kumar Gala

fdt: rework fdt_fixup_ethernet() to use env instead of bd_t

2008-08-21T00:07:43+00:00

Move to using the environment variables 'ethaddr', 'eth1addr', etc..
instead of bd->bi_enetaddr, bi_enet1addr, etc.

This makes the code a bit more flexible to the number of ethernet
interfaces.

Signed-off-by: Kumar Gala

Clean up usage of icache_disable/dcache_disable

2008-08-18T22:57:28+00:00

There is no point in disabling the icache on 7xx/74xx/86xx parts and not
also flushing the icache.  All callers of invalidate_l1_instruction_cache()
call icache_disable() right after.  Make it so icache_disable() calls
invalidate_l1_instruction_cache() for us.

Also, dcache_disable() already calls dcache_flush() so there is no point
in the explicit calls of dcache_flush().

Signed-off-by: Kumar Gala

POWERPC 86xx: Move BAT setup code to C

2008-08-11T21:53:59+00:00

This is needed because we will be possibly be locating
devices at physical addresses above 32bits, and the asm
preprocessing does not appear to deal with ULL constants
properly. We now call write_bat in lib_ppc/bat_rw.c.

Signed-off-by: Becky Bruce 
Acked-by: Jon Loeliger