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<title>u-boot.git/cpu/mpc8xxx/cpu.c, branch v2009.11</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>ppc/p4080: Add various p4080 related defines (and p4040)</title>
<updated>2009-09-24T17:05:28+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2009-03-19T07:39:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7e4259bba4c56536760e42d32dacfb3233f216fd'/>
<id>7e4259bba4c56536760e42d32dacfb3233f216fd</id>
<content type='text'>
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 &amp; p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 &amp; p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().</title>
<updated>2009-09-08T14:10:08+00:00</updated>
<author>
<name>Poonam Aggrwal</name>
<email>poonam.aggrwal@freescale.com</email>
</author>
<published>2009-09-03T14:12:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=21170c80a83f1e60ce7f6f83005e06a5c2d15a8e'/>
<id>21170c80a83f1e60ce7f6f83005e06a5c2d15a8e</id>
<content type='text'>
While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>ppc/85xx,86xx: Handling Unknown SOC version</title>
<updated>2009-09-08T14:10:08+00:00</updated>
<author>
<name>Poonam Aggrwal</name>
<email>poonam.aggrwal@freescale.com</email>
</author>
<published>2009-09-02T08:05:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=58442dc01e47cc8ce42af4f29486a34cad60b9d2'/>
<id>58442dc01e47cc8ce42af4f29486a34cad60b9d2</id>
<content type='text'>
Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>85xx: Added single core members of FSL P1xx/P2xx processors series</title>
<updated>2009-08-28T22:12:41+00:00</updated>
<author>
<name>Poonam Aggrwal</name>
<email>poonam.aggrwal@freescale.com</email>
</author>
<published>2009-08-20T13:27:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a713ba926b45da9a6f923f1ac9e60a66852e5f2d'/>
<id>a713ba926b45da9a6f923f1ac9e60a66852e5f2d</id>
<content type='text'>
P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>85xx: Added P1020 Processor Support.</title>
<updated>2009-08-28T22:12:39+00:00</updated>
<author>
<name>Poonam Aggrwal</name>
<email>poonam.aggrwal@freescale.com</email>
</author>
<published>2009-07-31T06:38:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=87c7661b42aa7672539b54b51d3d5c4013ec6f6c'/>
<id>87c7661b42aa7672539b54b51d3d5c4013ec6f6c</id>
<content type='text'>
P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx</title>
<updated>2009-08-28T22:12:38+00:00</updated>
<author>
<name>Poonam Aggrwal</name>
<email>poonam.aggrwal@freescale.com</email>
</author>
<published>2009-07-31T06:38:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0e870980a64584a591af775bb9c9fe9450124df9'/>
<id>0e870980a64584a591af775bb9c9fe9450124df9</id>
<content type='text'>
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
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<pre>
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>8xxx: Refactored common cpu specific code for 85xx/86xx into one file.</title>
<updated>2009-08-28T22:12:38+00:00</updated>
<author>
<name>Poonam Aggrwal</name>
<email>poonam.aggrwal@freescale.com</email>
</author>
<published>2009-07-31T06:37:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=18bacc2027f8531d8dec15ba8da3242dfb4e63f3'/>
<id>18bacc2027f8531d8dec15ba8da3242dfb4e63f3</id>
<content type='text'>
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
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<pre>
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</entry>
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