u-boot.git/cpu/mpc8xxx, branch v2008.10

Coding style cleanup, update CHANGELOG

2008-09-13T00:23:05Z

Signed-off-by: Wolfgang Denk

Fix compiler warning in mpc8xxx ddr code

2008-09-06T23:26:13Z

ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function ctrl_regs.c:523: note: 'caslat' was declared here Add a warning in DDR1 case if cas_latency isn't a value we know about. Signed-off-by: Kumar Gala Acked-by: Jean-Christophe PLAGNIOL-VILLARD

FSL DDR: Add DDR2 DIMM paramter support

2008-08-27T00:06:00Z

Compute DIMM parameters based upon the SPD information. Signed-off-by: James Yang Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala

FSL DDR: Add DDR1 DIMM paramter support

2008-08-27T00:05:59Z

Compute DIMM parameters based upon the SPD information in spd. Signed-off-by: James Yang Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala

FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

2008-08-27T00:05:58Z

The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang Signed-off-by: Jon Loeliger Signed-off-by: Becky Bruce Signed-off-by: Ed Swarthout Signed-off-by: Kumar Gala