u-boot.git/cpu/mpc8xxx, branch v2009.01

fsl ddr skip interleaving if not supported.

2008-12-04T04:47:19+00:00

Removed while(1) hang if memctl_intlv_ctl is set wrong.
Remove embedded tabs from strings.

Signed-off-by: Ed Swarthout 
Acked-by: Kumar Gala 
Acked-by: Andy Fleming

Add debug information for DDR controller registers

2008-10-18T19:54:05+00:00

Signed-off-by: Haiying Wang

Check DDR interleaving mode

2008-10-18T19:54:05+00:00

* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting

Signed-off-by: Haiying Wang

Pass dimm parameters to populate populate controller options

2008-10-18T19:54:04+00:00

Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang

Make DDR interleaving mode work correctly

2008-10-18T19:54:04+00:00

Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.

Signed-off-by: Haiying Wang

rename CFG_ macros to CONFIG_SYS

2008-10-18T19:54:03+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

Coding style cleanup, update CHANGELOG

2008-09-13T00:23:05+00:00

Signed-off-by: Wolfgang Denk

Fix compiler warning in mpc8xxx ddr code

2008-09-06T23:26:13+00:00

ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function
ctrl_regs.c:523: note: 'caslat' was declared here

Add a warning in DDR1 case if cas_latency isn't a value we know about.

Signed-off-by: Kumar Gala 
Acked-by: Jean-Christophe PLAGNIOL-VILLARD

FSL DDR: Add DDR2 DIMM paramter support

2008-08-27T00:06:00+00:00

Compute DIMM parameters based upon the SPD information.

Signed-off-by: James Yang 
Signed-off-by: Jon Loeliger 
Signed-off-by: Kumar Gala

FSL DDR: Add DDR1 DIMM paramter support

2008-08-27T00:05:59+00:00

Compute DIMM parameters based upon the SPD information in spd.

Signed-off-by: James Yang 
Signed-off-by: Jon Loeliger 
Signed-off-by: Kumar Gala