u-boot.git/cpu/mpc8xxx, branch v2009.03

fsl-ddr: Allow system to boot if we have more than 4G of memory

2009-02-17T00:05:55+00:00

Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report
an error and hang.  Instead of doing that since DDR is mapped in the
lowest priority LAWs we setup the DDR controller and the max amount
of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED)

Signed-off-by: Kumar Gala 
Acked-by: Becky Bruce

fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller

2009-02-17T00:05:50+00:00

If we only have one controller we can completely ignore how
memctl_intlv_ctl is set.  Otherwise other levels of code get confused
and think we have twice as much memory.

Signed-off-by: Kumar Gala

fsl-ddr: use the 1T timing as default configuration

2009-01-23T23:03:14+00:00

For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.

Signed-off-by: Dave Liu 
Acked-by: Andy Fleming

fsl-ddr: make the self refresh idle threshold configurable

2009-01-23T23:03:14+00:00

Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.

If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.

Signed-off-by: Dave Liu 
Acked-by: Andy Fleming

fsl-ddr: clean up the ddr code for DDR3 controller

2009-01-23T23:03:13+00:00

- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support

Signed-off-by: Dave Liu 
Acked-by: Andy Fleming

fsl-ddr: update the bit mask for DDR3 controller

2009-01-23T23:03:13+00:00

According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.

Signed-off-by: Dave Liu

fsl ddr skip interleaving if not supported.

2008-12-04T04:47:19+00:00

Removed while(1) hang if memctl_intlv_ctl is set wrong.
Remove embedded tabs from strings.

Signed-off-by: Ed Swarthout 
Acked-by: Kumar Gala 
Acked-by: Andy Fleming

Add debug information for DDR controller registers

2008-10-18T19:54:05+00:00

Signed-off-by: Haiying Wang

Check DDR interleaving mode

2008-10-18T19:54:05+00:00

* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting

Signed-off-by: Haiying Wang

Pass dimm parameters to populate populate controller options

2008-10-18T19:54:04+00:00

Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang