u-boot.git/cpu/mpc8xxx, branch v2009.06

fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT

2009-06-12T14:15:50+00:00

The ddr code computes most things as 64-bit quantities and had some places
in the middle that it was using phy_addr_t and phys_size_t.

Instead we use unsigned long long through out and only at the last stage of
setting the LAWs and reporting the amount of memory to the board code do we
truncate down to what we can cover via phys_size_t.

This has the added benefit that the DDR controller itself is always setup
the same way regardless of how much memory we have.  Its only the LAW
setup that limits what is visible to the system.

Signed-off-by: Kumar Gala

fsl-ddr: add the DDR3 SPD infrastructure

2009-03-30T18:33:50+00:00

- support mirrored DIMMs, not support register DIMMs
- test passed on P2020DS board with MT9JSF12872AY-1G1D1
- test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1

Signed-off-by: Dave Liu 
Signed-off-by: Travis Wheatley

fsl-ddr: Fix two bugs in the ddr infrastructure

2009-03-30T18:33:50+00:00

1. wr_lat
   UM said the total write latency for DDR2 is equal to
   WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1.
   so, the WR_LAT = CL - 1;
2. rd_to_pre
   we missed to add the ADD_LAT for DDR2 case.

Reported-by: Joakim Tjernlund 
Signed-off-by: Dave Liu

fsl-ddr: Allow system to boot if we have more than 4G of memory

2009-02-17T00:05:55+00:00

Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report
an error and hang.  Instead of doing that since DDR is mapped in the
lowest priority LAWs we setup the DDR controller and the max amount
of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED)

Signed-off-by: Kumar Gala 
Acked-by: Becky Bruce

fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller

2009-02-17T00:05:50+00:00

If we only have one controller we can completely ignore how
memctl_intlv_ctl is set.  Otherwise other levels of code get confused
and think we have twice as much memory.

Signed-off-by: Kumar Gala

fsl-ddr: use the 1T timing as default configuration

2009-01-23T23:03:14+00:00

For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.

Signed-off-by: Dave Liu 
Acked-by: Andy Fleming

fsl-ddr: make the self refresh idle threshold configurable

2009-01-23T23:03:14+00:00

Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.

If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.

Signed-off-by: Dave Liu 
Acked-by: Andy Fleming

fsl-ddr: clean up the ddr code for DDR3 controller

2009-01-23T23:03:13+00:00

- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support

Signed-off-by: Dave Liu 
Acked-by: Andy Fleming

fsl-ddr: update the bit mask for DDR3 controller

2009-01-23T23:03:13+00:00

According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.

Signed-off-by: Dave Liu

fsl ddr skip interleaving if not supported.

2008-12-04T04:47:19+00:00

Removed while(1) hang if memctl_intlv_ctl is set wrong.
Remove embedded tabs from strings.

Signed-off-by: Ed Swarthout 
Acked-by: Kumar Gala 
Acked-by: Andy Fleming