u-boot.git/cpu/mpc8xxx, branch v2009.11

fsl-ddr: Fix the chip-select interleaving issue

2009-11-12T14:09:49+00:00

commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
introduced one new bug to chip-select interleaving.

Single DDR controller also can do the chip-select
interleaving if there is dual-rank or qual-rank DIMMs.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

mpc8xxx: improve LAW error messages when setting up DDR

2009-10-16T15:21:39+00:00

When setting up the LAWs for the DDR, if there was an error,
you got the not-so-helpful error text "ERROR" and nothing
else.  Not only is it non-informative, but it is also
pretty frustrating trying to grep for "ERROR" in the source.

Signed-off-by: Paul Gortmaker 
Signed-off-by: Kumar Gala

ppc/p4080: Add various p4080 related defines (and p4040)

2009-09-24T17:05:28+00:00

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala

ppc/8xxx: Misc DDR related fixes

2009-09-16T02:30:08+00:00

* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print

Signed-off-by: Kumar Gala

ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().

2009-09-08T14:10:08+00:00

While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

ppc/85xx/86xx: Device tree fixup for number of cores

2009-09-08T14:10:08+00:00

Fixing the number of cores in the device tree based on the actual number of
cores on the system.  With this same device tree image can be used for dual
core and single core members of otherwise exactly same SOC.

For example:
* P2020RDB and P2010RDB
* P1020RDB and P1011RDB
* MPC8641D and MPC8641

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

ppc/85xx,86xx: Handling Unknown SOC version

2009-09-08T14:10:08+00:00

Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host

2009-09-08T14:10:07+00:00

Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.

Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.

Signed-off-by: Kumar Gala

ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist

2009-09-08T14:10:04+00:00

The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.

Signed-off-by: Kumar Gala

85xx: Added single core members of FSL P1xx/P2xx processors series

2009-08-28T22:12:41+00:00

P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala