u-boot.git/cpu/mpc8xxx, branch v2010.03

fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave

2010-01-05T19:50:07Z

In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala

fsl-ddr: add override for the Rtt_Wr

2010-01-05T19:49:27Z

Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala

fsl-ddr: add the override for write leveling

2010-01-05T19:49:10Z

add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala

fsl-ddr: Fix power-down timing settings

2010-01-05T19:49:10Z

1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: Dave Liu Signed-off-by: Kumar Gala

ppc/8xxx: Remove is_fsl_pci_agent

2010-01-05T19:49:07Z

All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala

ppc/8xxx: Don't use pci_cfg on FSL_CORENET platforms

2010-01-05T19:49:03Z

The FSL_CORENET platforms use a completely different means to determine which PCIe port is enabled as well as if its a host or agent/end-point. Signed-off-by: Kumar Gala

fsl-ddr: Fix the chip-select interleaving issue

2009-11-12T14:09:49Z

commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3 introduced one new bug to chip-select interleaving. Single DDR controller also can do the chip-select interleaving if there is dual-rank or qual-rank DIMMs. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala

mpc8xxx: improve LAW error messages when setting up DDR

2009-10-16T15:21:39Z

When setting up the LAWs for the DDR, if there was an error, you got the not-so-helpful error text "ERROR" and nothing else. Not only is it non-informative, but it is also pretty frustrating trying to grep for "ERROR" in the source. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala

ppc/p4080: Add various p4080 related defines (and p4040)

2009-09-24T17:05:28Z

There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala

ppc/8xxx: Misc DDR related fixes

2009-09-16T02:30:08Z

* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong * Fix the format string to match size in a debug print Signed-off-by: Kumar Gala