u-boot.git/cpu/ppc4xx/cpu.c, branch u-boot-2009.11.y Unnamed repository; edit this file 'description' to name the repository. ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT 2010-01-23T16:53:11+00:00 Felix Radensky felix@embedded-sol.com 2010-01-19T15:37:13+00:00 17ab3057bde25208af71326c0ff213d05eadb318 Bootstrap options G and F are reported incorrectly (G instead of F and vice versa). This patch fixes this. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de> 
Bootstrap options G and F are reported incorrectly (G instead
of F and vice versa). This patch fixes this.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Print PCI synchronous clock frequency upon bootup 2009-10-23T14:04:45+00:00 Stefan Roese sr@denx.de 2009-10-19T12:44:11+00:00 08c6a2628478ace808b3767db17e4148cac5a7fb Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal synchronous PCI clock. Knowledge about the currently configured value might be helpful. So let's print it out upon bootup. Signed-off-by: Stefan Roese <sr@denx.de> 
Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal
synchronous PCI clock. Knowledge about the currently configured
value might be helpful. So let's print it out upon bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Add PPC405EX(r) Rev D support 2009-10-07T07:14:27+00:00 Stefan Roese sr@denx.de 2009-10-06T05:21:08+00:00 56f14818f66c68a8b9e45925f29ceb974405ad48 Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older 405EX(r) parts. Here a list: 0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec 0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec Since there are only a few older parts in the field, this patch now changes the PVR's above to represent the new Rev D versions. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Phong Vo" <pvo@amcc.com> 
Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:

0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec

Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phong Vo" <pvo@amcc.com>
ppc4xx: Big cleanup of PPC4xx defines 2009-09-11T08:35:58+00:00 Stefan Roese sr@denx.de 2009-09-09T14:25:29+00:00 d1c3b27525b664e8c4db6bb173eed51bfc8220de This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de> 
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chips 2009-07-30T05:22:18+00:00 Stefan Roese sr@denx.de 2009-07-29T06:45:27+00:00 89bcc4875007ef6608297dc11e7a0d1fbd9900d2 This patch is based on a diff created by Phong Vo from AMCC. Signed-off-by: Phong Vo <pvo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de> 
This patch is based on a diff created by Phong Vo from AMCC.

Signed-off-by: Phong Vo <pvo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Replace 4xx lowercase SPR references 2009-07-24T04:47:17+00:00 Matthias Fuchs matthias.fuchs@esd.eu 2009-07-22T15:27:56+00:00 58ea142fb2e969f32306c8da1dabfaebd6fa141a Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de> 
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Remove compilation warning "pci_async_enabled defined but not used" 2009-07-08T08:59:07+00:00 Stefan Roese sr@denx.de 2009-07-06T09:44:33+00:00 20b3c4b528606d51799aed5e4c71783720cd2b72 Signed-off-by: Stefan Roese <sr@denx.de> 
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Remove PCI async bootup message if PCI is not used 2009-06-12T18:39:52+00:00 Stefan Roese sr@denx.de 2009-05-27T08:34:32+00:00 1bbae2b816d4ed38db2ebf42166a973b1ffc0df7 Signed-off-by: Stefan Roese <sr@denx.de> 
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Add "booting from NAND" to 4xx NAND-booting targets 2009-04-16T07:12:08+00:00 Stefan Roese sr@denx.de 2009-04-15T08:50:48+00:00 cf9409885cbe01405bad76790e99f8adf3351f4d This additional text in the bootup log helps to see if the board is configured for NAND-booting. Especially helpful for boards that can boot from NOR and NAND (e.g. most of the AMCC eval boards). Signed-off-by: Stefan Roese <sr@denx.de> 
This additional text in the bootup log helps to see if the board is
configured for NAND-booting. Especially helpful for boards that can
boot from NOR and NAND (e.g. most of the AMCC eval boards).

Signed-off-by: Stefan Roese <sr@denx.de>
Coding style cleanup, update CHANGELOG. 2008-12-16T00:02:17+00:00 Wolfgang Denk wd@denx.de 2008-12-16T00:02:17+00:00 455ae7e87f67c44e6aea68865c83acadd3fcd36c Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>