u-boot.git/cpu/ppc4xx/cpu.c, branch v1.3.2

ppc4xx: Enable 405EX PCIe UTL register configuration

2007-11-16T13:16:54+00:00

Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.

Signed-off-by: Stefan Roese

ppc4xx: Make output a little shorter on I2C bootrom detection

2007-11-09T11:18:54+00:00

Most 4xx PPC capable of using an I2C bootrom for bootstrap setting
already print a line with the information which I2C bootrom is
used for bootstrap configuration. So we don't need this extra line
with "I2C boot EEPROM en-/dis-abled".

This patch also has a little code cleanup integrated.

Signed-off-by: Stefan Roese

ppc4xx: Add PPC405EX support

2007-10-31T20:20:49+00:00

Signed-off-by: Stefan Roese

[PATCH] Fix ppc4xx bootstrap letter displayed on startup

2007-06-04T06:36:05+00:00

The attached patch is mainly cosmetic, allowing u-boot to
display the correct bootstrap option letter according to the
datasheets.

The original patch was extended with 405EZ support by Stefan
Roese.

Signed-off-by: Benoit Monin 
Signed-off-by: Stefan Roese

ppc4xx: Add output for bootrom location to 405EZ ports

2007-04-18T10:05:59+00:00

Now 405EZ ports also show upon bootup from which boot device
they are configured to boot:

U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)

CPU:   AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
       Bootstrap Option E - Boot ROM Location EBC (32 bits)
       16 kB I-Cache 16 kB D-Cache
Board: Acadia - AMCC PPC405EZ Evaluation Board

Signed-off-by: Stefan Roese

[PATCH] Add AMCC PPC405EZ support

2007-03-21T12:38:59+00:00

This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.

Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.

Signed-off-by: Stefan Roese

[PATCH] Correctly display PCI arbiter en-/disabled on some 4xx boards

2007-02-02T11:44:22+00:00

Previously the strapping DCR/SDR was read to determine if the internal PCI
arbiter is enabled or not. This strapping bit can be overridden, so now
the current status is read from the correct DCR/SDR register.

Signed-off-by: Stefan Roese

[PATCH] Update 440EPx/440GRx cpu detection

2007-01-31T15:56:10+00:00

Signed-off-by: Stefan Roese

[PATCH] Fix 440SPe rev B detection from previous patch

2007-01-15T08:46:29+00:00

Signed-off-by: Stefan Roese

[PATCH] Update 440SP(e) cpu revisions

2007-01-13T07:01:03+00:00

Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.

Signed-off-by: Stefan Roese