This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359
which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally
disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set.

Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the PLL to run the system with a CPU
frequency of 667MHz and PLB frequency of 166MHz, without the need for an
external EEPROM.

Signed-off-by: Mike Nuss <mike@terascala.com>
Acked-by: Stefan Roese <sr@denx.de>

This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>

In an attmemt to clean up the 4xx start.S file, I removed the enabling
of the internal 405EP PCI arbiter. This is needed for multiple other
405EP platforms, like most of the esd 405EP. Now the internal PCI
arbiter is enabled again per default as it has been before.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

Added memory, CPU, UART, I2C and SPR POST tests for PPC440.

Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--

This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.

Signed-off-by: Stefan Roese <sr@denx.de>