u-boot.git/cpu/ppc4xx/cpu_init.c, branch v1.3.4

ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic

2008-06-30T13:20:41+00:00

This patch implements a fix provided by AMCC so that the lockup upon
simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur
anymore:

Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2]
(bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG,
USB 2.0 host and SATA.

This errata is not officially available yet. I'll update the comment
to add the errata number later.

Signed-off-by: Stefan Roese

ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling

2008-06-03T18:20:50+00:00

This patch (Part 1 of 2):

* Rolls up a suite of changes to enable correct primordial stack and
  global data handling when the data cache is used for such a purpose
  for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).

* Related to the first, unifies DDR2 SDRAM and ECC initialization by
  eliminating redundant ECC initialization implementations and moving
  redundant SDRAM initialization out of board code into shared 4xx
  code.

* Enables MCSR visibility on the 405EX(r).

* Enables the use of the data cache for initial RAM on
  both AMCC's Kilauea and Makalu and removes a redundant
  CFG_POST_MEMORY flag from each board's CONFIG_POST value.

  - Removed, per Stefan Roese's request, defunct memory.c file for
    Makalu and rolled sdram_init from it into makalu.c.

With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.

Signed-off-by: Grant Erickson 
Signed-off-by: Stefan Roese

ppc4xx: PPC405EP Set EMAC noise filter bits

2008-03-27T09:47:28+00:00

This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359
which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally
disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set.

Signed-off-by: Markus Brunner 
Signed-off-by: Stefan Roese

ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx

2008-03-27T09:38:54+00:00

On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the PLL to run the system with a CPU
frequency of 667MHz and PLB frequency of 166MHz, without the need for an
external EEPROM.

Signed-off-by: Mike Nuss 
Acked-by: Stefan Roese

ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)

2008-03-15T06:28:04+00:00

This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese

ppc4xx: Enable 405EP PCI arbiter per default on all boards

2007-12-28T15:39:15+00:00

In an attmemt to clean up the 4xx start.S file, I removed the enabling
of the internal 405EP PCI arbiter. This is needed for multiple other
405EP platforms, like most of the esd 405EP. Now the internal PCI
arbiter is enabled again per default as it has been before.

Signed-off-by: Stefan Roese 
Acked-by: Matthias Fuchs

ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP)

2007-12-28T15:39:11+00:00

Signed-off-by: Stefan Roese 
Acked-by: Matthias Fuchs

ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms

2007-11-15T13:23:55+00:00

- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h

Signed-off-by: Stefan Roese

ppc4xx: Add PPC405EX support

2007-10-31T20:20:49+00:00

Signed-off-by: Stefan Roese

Coding stylke cleanup; rebuild CHANGELOG

2007-06-22T21:59:00+00:00