u-boot.git/cpu/ppc4xx/cpu_init.c, branch v2009.11

ppc4xx: Add function to check and dynamically change PCI sync clock

2009-10-23T14:04:36+00:00

PPC440EP(x)/PPC440GR(x):
In asynchronous PCI mode, the synchronous PCI clock must meet
certain requirements. The following equation describes the
relationship that must be maintained between the asynchronous PCI
clock and synchronous PCI clock. Select an appropriate PCI:PLB
ratio to maintain the relationship:

AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz

This patch now adds a function to check and reconfigure the sync
PCI clock to meet this requirement. This is in preparation for
some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
function to not violate the PCI clocking rules.

Signed-off-by: Stefan Roese

ppc_4xx: Apply new HW register names

2009-10-07T07:15:20+00:00

Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.

Signed-off-by: Niklaus Giger 
Signed-off-by: Stefan Roese

ppc4xx: Big cleanup of PPC4xx defines

2009-09-11T08:35:58+00:00

This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese

ppc4xx: Replace 4xx lowercase SPR references

2009-07-24T04:47:17+00:00

Signed-off-by: Matthias Fuchs 
Signed-off-by: Stefan Roese

ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()

2009-07-10T06:26:03+00:00

This patch moves some basic PCI initialisation from the 4xx cpu_init_f()
to cpu/ppc4xx/4xx_pci.c.

The original cpu_init_f() function enabled the 405EP's internal arbiter
in all situations. Also the HCE bit in cpc0_pci is always set.
The first is not really wanted for PCI adapter designs and the latter
is a general bug for PCI adapter U-Boots. Because it enables
PCI configuration by the system CPU even when the PCI configuration has
not been setup by the 405EP. The one and only correct place is
in pci_405gp_init() (see "Set HCE bit" comment).

So for compatibility reasons the arbiter is still enabled in any case,
but from weak pci_pre_init() so that it can be replaced by board specific
code.

Signed-off-by: Matthias Fuchs 
Signed-off-by: Stefan Roese

ppc4xx: Don't write the MAC address into the internal SoC registers

2009-03-20T21:39:14+00:00

Remove this code. It's not needed. The 4xx EMAC driver stores the MAC
addresses into the SoC registers instead.

Signed-off-by: Stefan Roese

cpu/: get mac address from environment

2009-03-20T21:39:11+00:00

The environment is the canonical storage location of the mac address, so
we're killing off the global data location and moving everything to
querying the env directly.

The cpus that get converted here:
	at91rm9200
	mpc512x
	mpc5xxx
	mpc8260
	mpc8xx
	ppc4xx

Signed-off-by: Mike Frysinger 
CC: Ben Warren 
CC: John Rigby 
CC: Stefan Roese

rename CFG_ macros to CONFIG_SYS

2008-10-18T19:54:03+00:00

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD

ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patch

2008-08-21T09:05:03+00:00

This patch fixes some minor issues introduced with the patch:
ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika:

- Rework memory-queue and PLB arbiter optimization code, that the
  local variable is not needed anymore. This removes one #ifdef.
- Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead
  of XXX+ 0x01). This was not introduced by Prodyut, just a
  copy-paste problem.

Signed-off-by: Stefan Roese

ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,

2008-08-21T08:31:16+00:00

	PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by: Prodyut Hazarika 
Signed-off-by: Stefan Roese