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<title>u-boot.git/cpu/ppc4xx/start.S, branch v2009.03-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/cpu/ppc4xx/start.S?h=v2009.03-rc2</id>
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<updated>2008-12-16T00:02:17Z</updated>
<entry>
<title>Coding style cleanup, update CHANGELOG.</title>
<updated>2008-12-16T00:02:17Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-12-16T00:02:17Z</published>
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<id>urn:sha1:455ae7e87f67c44e6aea68865c83acadd3fcd36c</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
<entry>
<title>Update U-Boot's build timestamp on every compile</title>
<updated>2008-12-06T22:36:43Z</updated>
<author>
<name>Peter Tyser</name>
<email>ptyser@xes-inc.com</email>
</author>
<published>2008-11-03T15:30:59Z</published>
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<id>urn:sha1:561858ee7d0274c3e89dc98d4d0698cb6fcf6fd9</id>
<content type='text'>
Use the GNU 'date' command to auto-generate a new U-Boot
timestamp on every compile.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization</title>
<updated>2008-11-21T10:02:04Z</updated>
<author>
<name>Dave Mitchell</name>
<email>dmitch71@gmail.com</email>
</author>
<published>2008-11-20T20:09:50Z</published>
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<id>urn:sha1:ddf45cc758d394591fb9bcdcbe96530f733f2bce</id>
<content type='text'>
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.

Adjusted internal SRAM initialization to match updated user
manual recommendation.

OCM &amp; ISRAM are now mapped as follows:
        physical        virtual         size
ISRAM   0x4_0000_0000   0xE300_0000     256k
OCM     0x4_0004_0000   0xE304_0000     64k

A single TLB was used for this mapping.

Signed-off-by: Dave Mitchell &lt;dmitch71@gmail.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs</title>
<updated>2008-11-21T09:52:33Z</updated>
<author>
<name>Dave Mitchell</name>
<email>dmitch71@gmail.com</email>
</author>
<published>2008-11-20T20:00:49Z</published>
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<id>urn:sha1:b14ca4b61a681f75f3125676e09d7ce6af66e927</id>
<content type='text'>
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.

Signed-off-by: Dave Mitchell &lt;dmitch71@gmail.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Clear all potentially pending exceptions in MCSR</title>
<updated>2008-11-20T10:48:53Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-11-20T10:46:20Z</published>
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<id>urn:sha1:25fb4eaaeab3f8866020818f4729d990dcc91cf0</id>
<content type='text'>
This is needed on Canyonlands which still has an exception pending
while running relocate_code(). This leads to a failure after trap_init()
is moved to the top of board_init_r().

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Generic architecture for xilinx ppc405(v3)</title>
<updated>2008-10-24T15:26:09Z</updated>
<author>
<name>Ricardo Ribalda Delgado</name>
<email>ricardo.ribalda@uam.es</email>
</author>
<published>2008-10-21T16:29:46Z</published>
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<id>urn:sha1:1f4d53260ec6f8f122aed75cce7c757d97a551e0</id>
<content type='text'>
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.

Any custom xilinx ppc405 board can be added very easily with no code
duplicity.

This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h

This patch is prepared to work with the latest version of EDK (10.1)

Signed-off-by: Ricardo Ribalda Delgado &lt;ricardo.ribalda@uam.es&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>rename CFG_ macros to CONFIG_SYS</title>
<updated>2008-10-18T19:54:03Z</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2008-10-16T13:01:15Z</published>
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<id>urn:sha1:6d0f6bcf337c5261c08fabe12982178c2c489d76</id>
<content type='text'>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Add initial 460SX defines for the cpu/ppc4xx directory.</title>
<updated>2008-07-11T11:18:12Z</updated>
<author>
<name>Feng Kan</name>
<email>fkan@amcc.com</email>
</author>
<published>2008-07-09T05:47:31Z</published>
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<id>urn:sha1:7d30793685efcada183891c78fc892e6c9ba50c7</id>
<content type='text'>
Signed-off-by: Feng Kan &lt;fkan@amcc.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Remove superfluous dram_init() call or replace it by initdram()</title>
<updated>2008-06-03T18:22:19Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-06-02T15:37:28Z</published>
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<id>urn:sha1:bbeff30cbd1c5d551eb0ad1c2239ec01844c0b0a</id>
<content type='text'>
Historically the 405 U-Boot port had a dram_init() call in early init
stage. This function was still called from start.S and most of the time
coded in assembler. This is not needed anymore (since a long time) and
boards should implement the common initdram() function in C instead.

This patch now removed the dram_init() call from start.S and removes the
empty implementations that are scattered through most of the 405 board
ports. Some older board ports really implement this dram_init() though.
These are:

csb272
csb472
ERIC
EXBITGEN
W7OLMC
W7OLMG

I changed those boards to call this assembler dram_init() function now
from their board specific initdram() instead. This *should* work, but please
test again on those platforms. And it is perhaps a good idea that those
boards use some common 405 SDRAM initialization code from cpu/ppc4xx at
some time. So further patches welcome here.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S</title>
<updated>2008-06-03T18:21:49Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-06-02T12:35:44Z</published>
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<id>urn:sha1:64852d09e06dd6db2b2db2a3c59bc2db176a54d6</id>
<content type='text'>
This patch consolidates the 405 and 440 parts of the NAND booting code
selected via CONFIG_NAND_SPL. Now common code is used to initialize the
SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
Only *after* running from this location, nand_boot() is called.

Please note that the initsdram() call is now moved from nand_boot.c
to start.S. I experienced problems with some boards like Kilauea
(405EX), which don't have internal SRAM (OCM) and relocation needs to
be done to SDRAM before the NAND controller can get accessed. When
initdram() is called later on in nand_boot(), this can lead to problems
with variables in the bss sections like nand_ecc_pos[].

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
</entry>
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