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<title>u-boot.git/cpu/ppc4xx, branch v2008.10</title>
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<id>http://cgit.235523.xyz/u-boot.git/atom/cpu/ppc4xx?h=v2008.10</id>
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<updated>2008-10-17T11:02:42Z</updated>
<entry>
<title>ppc4xx: PPC44x MQ initialization</title>
<updated>2008-10-17T11:02:42Z</updated>
<author>
<name>Yuri Tikhonov</name>
<email>yur@emcraft.com</email>
</author>
<published>2008-10-17T10:54:18Z</published>
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<id>urn:sha1:bf29e0ea0af03d593c64614136acc723a7a022a2</id>
<content type='text'>
Set the MQ Read Passing &amp; MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).

Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.

Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.

Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change</title>
<updated>2008-10-08T09:36:23Z</updated>
<author>
<name>Adam Graham</name>
<email>agraham@amcc.com</email>
</author>
<published>2008-10-06T17:16:13Z</published>
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<id>urn:sha1:f8a00dea841d5d75de1f8e8107e90ee1beeddf5f</id>
<content type='text'>
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham &lt;agraham@amcc.com&gt;
Signed-off-by: Victor Gallardo &lt;vgallardo@amcc.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>Revert "ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)"</title>
<updated>2008-09-22T09:06:50Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-09-22T09:06:50Z</published>
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<id>urn:sha1:023824549a370bd185d7129d9a6c86f9be7b86a8</id>
<content type='text'>
This reverts commit 3eec160a3a405b29ce9c06920f6427b9047dd8a8.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)</title>
<updated>2008-09-16T18:16:31Z</updated>
<author>
<name>Victor Gallardo</name>
<email>vgallardo@amcc.com</email>
</author>
<published>2008-09-16T13:59:13Z</published>
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<id>urn:sha1:3eec160a3a405b29ce9c06920f6427b9047dd8a8</id>
<content type='text'>
Signed-off-by: Victor Gallardo &lt;vgallardo@amcc.com&gt;
Signed-off-by: Adam Graham &lt;agraham@amcc.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports</title>
<updated>2008-09-12T05:12:33Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-09-10T14:53:47Z</published>
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<id>urn:sha1:7bf5ecfa50722a9feb45ea8f04da75f5d406f20b</id>
<content type='text'>
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].

The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Remove CONFIG_CS8952_PHY define</title>
<updated>2008-09-08T08:27:56Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-09-08T08:01:48Z</published>
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<id>urn:sha1:f071f01fd09e9bf1cf09de37a7416aacce71bae1</id>
<content type='text'>
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Fix compilation warning for PIP405</title>
<updated>2008-09-08T08:27:51Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-09-05T12:11:40Z</published>
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<id>urn:sha1:6ca8646c1860bba74326bf916a5a3389a5c0d3b5</id>
<content type='text'>
This patch fixes a compilation warning for the PIP405 board. It moves the
#ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
occur anymore. I am a little unsure if this #ifdef is at the correct
place now or if it could be removed completely. This needs to get
tested on the PIP405 board.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Fix compilation warning for canyonlands &amp; glacier</title>
<updated>2008-09-08T08:27:46Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-09-05T12:09:09Z</published>
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<id>urn:sha1:725b53ac61f4df3026b8f6489ef0080fd27d3816</id>
<content type='text'>
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Add support for GPCS, SGMII and M88E1112 PHY</title>
<updated>2008-09-05T10:21:16Z</updated>
<author>
<name>Victor Gallardo</name>
<email>vgallardo@amcc.com</email>
</author>
<published>2008-09-05T06:49:36Z</published>
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<id>urn:sha1:78d78236896d62bb8ca7302af38d8f1493eb2651</id>
<content type='text'>
This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.

Signed-off-by: Victor Gallardo &lt;vgallardo@amcc.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines</title>
<updated>2008-09-05T10:04:16Z</updated>
<author>
<name>Adam Graham</name>
<email>agraham@amcc.com</email>
</author>
<published>2008-09-03T19:26:59Z</published>
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<id>urn:sha1:f6b6c45840f9b4671d2d97243a12a1f3ffb64765</id>
<content type='text'>
Signed-off-by: Adam Graham &lt;agraham@amcc.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
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