Signed-off-by: Detlev Zundel <dzu@denx.de>
__attribute__ follows gcc's documented syntax and is generally more common than __attribute. This change is only asthetic and should not affect functionality. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This additional text in the bootup log helps to see if the board is configured for NAND-booting. Especially helpful for boards that can boot from NOR and NAND (e.g. most of the AMCC eval boards). Signed-off-by: Stefan Roese <sr@denx.de>
Remove this code. It's not needed. The 4xx EMAC driver stores the MAC addresses into the SoC registers instead. Signed-off-by: Stefan Roese <sr@denx.de>
The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. The cpus that get converted here: at91rm9200 mpc512x mpc5xxx mpc8260 mpc8xx ppc4xx Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com> CC: John Rigby <jrigby@freescale.com> CC: Stefan Roese <sr@denx.de>
PCI outbound address map configuration doesn't match the PCI memory address range covered by appropriate TLB entry configuration for canyonlands causing machine check exceptions while accessing PCI memory regions. This patch provides a fix for this issue. Kazuaki Ichinohe observed and reported this issue while testing display output with PCI ATI video card on canyonlands. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes a problem recently seen on some 4xx platforms. For example on Kilauea PCIe slot #0. Signed-off-by: Stefan Roese <sr@denx.de>
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2 initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits. Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com> Signed-off-by: Stefan Roese <sr@denx.de>
The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent between the two current users (lib_ppc/board.c, 44x SPD DDR2). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>