u-boot.git/cpu/ppc4xx, branch v2009.11.1

ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs

2010-01-23T16:53:22+00:00

On platforms where SPD EEPROM and another EEPROM have adjacent
I2C addresses SPD_EEPROM_ADDRESS should be defined as a single
element array, otherwise DDR2 setup code would fail with the
following error:

ERROR: Unknown DIMM detected in slot 1

However, fixing SPD_EEPROM_ADDRESS would result in another
error:

ERROR: DIMM's DDR1 and DDR2 type can not be mixed.

This happens because initdram() routine does not explicitly
initialize dimm_populated array. This patch fixes the problem.

Signed-off-by: Felix Radensky 
Signed-off-by: Stefan Roese

ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT

2010-01-23T16:53:11+00:00

Bootstrap options G and F are reported incorrectly (G instead
of F and vice versa). This patch fixes this.

Signed-off-by: Felix Radensky 
Signed-off-by: Stefan Roese

ppc4xx: 44x_spd_ddr2.c: Fix register macro ECCCR -> ECCES (SDRAM_ECCES)

2009-11-09T12:31:38+00:00

This error only appears when DEBUG is enabled in this driver. That's why
it went unnoticed till now.

Signed-off-by: Stefan Roese

ppc4xx: Print PCI synchronous clock frequency upon bootup

2009-10-23T14:04:45+00:00

Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal
synchronous PCI clock. Knowledge about the currently configured
value might be helpful. So let's print it out upon bootup.

Signed-off-by: Stefan Roese

ppc4xx: Add function to check and dynamically change PCI sync clock

2009-10-23T14:04:36+00:00

PPC440EP(x)/PPC440GR(x):
In asynchronous PCI mode, the synchronous PCI clock must meet
certain requirements. The following equation describes the
relationship that must be maintained between the asynchronous PCI
clock and synchronous PCI clock. Select an appropriate PCI:PLB
ratio to maintain the relationship:

AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz

This patch now adds a function to check and reconfigure the sync
PCI clock to meet this requirement. This is in preparation for
some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
function to not violate the PCI clocking rules.

Signed-off-by: Stefan Roese

ppc4xx: Update flash size in reg property of the NOR flash node

2009-10-23T13:56:32+00:00

Till now only the ranges in the ebc node are updated with the values
currently configured in the PPC4xx EBC controller. With this patch now
the NOR flash size is updated in the device tree blob as well. This is
done by scanning the compatible nodes "cfi-flash" and "jedec-flash"
for the correct chip select number.

This size fixup is enabled for all AMCC eval board right now. Other
4xx boards may want to enable it as well, if this problem with multiple
NOR FLASH sizes exists.

Signed-off-by: Stefan Roese 
Cc: Wolfgang Denk

cpu/ppc4xx/fdt.c: avoid strcpy() to constant string

2009-10-23T13:50:22+00:00

strcpy() was iused with the target address being a pointer to a
constant string, which potentially is read-only. Use a (writable)
array of characters instead.

Signed-off-by: Wolfgang Denk 
Signed-off-by: Stefan Roese

Merge branch 'reloc'

2009-10-08T22:03:18+00:00

relocation: Do not relocate NULL pointers.

2009-10-08T07:33:36+00:00

NULL is an absolute value and should not be relocated.
After this correction code like:
 void weak_fun(void) __attribute__((weak));
 printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.

Signed-off-by: Joakim Tjernlund

ppc4xx: Rework cmd reginfo

2009-10-07T07:15:26+00:00

The command "reginfo" got an overhaul for the ppc4xx. It dumps all the
relevant HW configuration registers (address, symbolic name, content).
This allows to easily detect errors in *.h files and changes in the HW
configuration.

Signed-off-by: Niklaus Giger 
Signed-off-by: Stefan Roese