Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>

start.S:183:1: warning: "ICMR" redefined
In file included from start.S:33:
include/asm/arch/pxa-regs.h:935:1: warning: this is the location of the previous definition
start.S:187:1: warning: "RCSR" redefined
...

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>

The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>

CFG_MONAHANS_TURBO_RUN_MODE_RATIO for configuring the Monahans core
frequency.

Code cleanup.

Controller.

 * Debug message can be turned on and off.
 * Waiting for events now times out.
 * Implemented RESET command.
 * Added appropriate nand_bbt_descriptor and nand_oobinfo.

Remaining Problems:
 * Read Status still behaves weird an returns invalid stuff sometimes.
 * ECC Placement does not respect our scheme in nand_oobinfo.