u-boot.git/cpu, branch LABEL_2006_04_18_1106 Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/u-boot.git/atom/cpu?h=LABEL_2006_04_18_1106 2006-04-18T09:05:03Z MPC5200: enable snooping of DMA transactions on XLB even if no PCI 2006-04-18T09:05:03Z Wolfgang Denk wd@pollux.denx.de 2006-04-18T09:05:03Z urn:sha1:8419c013048b1f15f3fa2fc7c0463d860a04ee3e is configured; othrwise DMA accesses aren't cache coherent which causes for example USB to fail. Some code cleanup 2006-04-16T08:51:58Z Wolfgang Denk wd@pollux.denx.de 2006-04-16T08:51:58Z urn:sha1:cf48eb9abd76e5a056937a4e49be094826026abc Fix Lite500B support: Merge with /home/raj/git/u-boot.l5200b_pci 2006-04-06T08:42:23Z Wolfgang Denk wd@pollux.denx.de 2006-04-06T08:42:23Z urn:sha1:9bc97a3d91bf3287b593afa2a5b9e3bb07c9de5c Merge with /home/sr/git/u-boot/4xx-sdram 2006-04-05T21:55:15Z Wolfgang Denk wd@pollux.denx.de 2006-04-05T21:55:15Z urn:sha1:197b049b8b8a488384f351b988dd15f78830ba4e Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S 2006-04-03T13:46:10Z Wolfgang Denk wd@nyx.denx.de 2006-04-03T13:46:10Z urn:sha1:db28ddb4da7387f4658ae5d032263258e53a1f37 Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473] GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31T16:32:53Z Wolfgang Denk wd@pollux.denx.de 2006-03-31T16:32:53Z urn:sha1:d87080b721e4f8dca977af7571c5338ae7bb8db7 Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) 2006-03-31T12:32:07Z Stefan Roese sr@denx.de 2006-03-17T09:28:24Z urn:sha1:62534beb2fdd67490c3723f22b8982e7d64fc104 405 SDRAM: - The SDRAM parameters can now be defined in the board config file and the 405 SDRAM controller values will be calculated upon bootup (see PPChameleonEVB). When those settings are not defined in the board config file, the register setup will be as it is now, so this implementation should not break any current design using this code. Thanks to Andrea Marson from DAVE for this patch. 440 DDR: - Added function sdram_tr1_set to auto calculate the TR1 value for the DDR. - Added ECC support (see p3p440). Patch by Stefan Roese, 17 Mar 2006 Set SDelay register in the DDR controller for the MPC5200B chip. 2006-03-29T11:17:09Z Rafal Jaworowski raj@pollux.denx.de 2006-03-29T11:17:09Z urn:sha1:b66a9383421805c705654ce9456ec28c202819fb Merge with http://www.denx.de/git/u-boot.git 2006-03-24T14:43:16Z Markus Klotzbuecher mk@denx.de 2006-03-24T14:43:16Z urn:sha1:2770bcb21c82835a5351176e5b2a9221d7fc8ef9 Added config options CFG_MONAHANS_RUN_MODE_OSC_RATIO and 2006-03-24T13:35:25Z Markus Klotzbuecher mk@denx.de 2006-03-24T13:35:25Z urn:sha1:40b0bafbb282a8fd2d705be0623948ff551bf26a CFG_MONAHANS_TURBO_RUN_MODE_RATIO for configuring the Monahans core frequency.