The L2 size detection code was a bit confusing and we kept having to add
code to it to handle new processors.  Change the sense of detection so we
look for the older processors that aren't changing.

Also added support for 1M cache size on 8572.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Some boards that have external 16550 UARTs don't have a direct
tie between bi_busfreq and the clock used for the UARTs.  Boards
that do have such a tie should set CFG_NS16550_CLK to be
get_bus_freq(0) -- which most of them do already.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>

With a page size of BOOKE_PAGESZ_16M, both the real and effective
addresses must be multiples of 16MB.  The hardware silently truncates
them so the code happens to work.  This patch clarifies the situation
by establishing addresses that the hardware doesn't need to truncate.

Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

Delete the crypto node if not on an E-processor.  If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

ARM DaVinci: Remove extern phy_t declaration by moving
code to proper place.

Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>