Reference manual states that MxMR[MAD] increment is the indication
of write to UPM array is complete. Honour that. Also, make the dummy
write explicit.

also fix the comment.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.

lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.

Signed-off-by: Nick Spence <nick.spence@freescale.com>

For some reason we duplicated the majority of code in lib_ppc/interrupts.c
Not know how that happened, but there is no good reason for it.

Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the
MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
correct. There seems to be an error in the 8544 RM.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>

Switch to the standard CFG_HZ=1000 value, while at it, minor white-space
cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads,
provides 2% or 0.4% precision depending on the
CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s
boot-delay.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>

On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>