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<title>u-boot.git/cpu, branch v2009.06-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>85xx: bugfix for reading maximum TLB size on mpc85xx</title>
<updated>2009-06-09T20:58:18+00:00</updated>
<author>
<name>Fredrik Arnerup</name>
<email>fredrik.arnerup@edgeware.tv</email>
</author>
<published>2009-06-02T21:27:10+00:00</published>
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<content type='text'>
The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits.
This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum
(256 MB)
which made u-boot hang in board_init_f() when trying to create a new stack
in RAM.
I have an mpc8540 with one 1GB dimm.

Signed-off-by: Fredrik Arnerup &lt;fredrik.arnerup@edgeware.tv&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Acked-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
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<pre>
The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits.
This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum
(256 MB)
which made u-boot hang in board_init_f() when trying to create a new stack
in RAM.
I have an mpc8540 with one 1GB dimm.

Signed-off-by: Fredrik Arnerup &lt;fredrik.arnerup@edgeware.tv&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Acked-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>ppc4xx: Fix problem with ECC ordering for PPC4xx NDFC platforms</title>
<updated>2009-05-23T10:51:39+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2009-05-20T08:58:02+00:00</published>
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This patch now uses the correct ECC byte order (Smart Media - SMC)
to be used on the 4xx NAND FLASH driver. Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.

Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in
drivers/mtd/nand/nand_ecc.c for correct operation. This is done with
a seperate patch.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
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<pre>
This patch now uses the correct ECC byte order (Smart Media - SMC)
to be used on the 4xx NAND FLASH driver. Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.

Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in
drivers/mtd/nand/nand_ecc.c for correct operation. This is done with
a seperate patch.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
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</entry>
<entry>
<title>ppc4xx: Move definition for PPC4xx NAND FLASH controller to header</title>
<updated>2009-05-23T10:51:39+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2009-05-20T08:58:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5d841fac8249a2b3f9a814da2140132be0a9f60d'/>
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<content type='text'>
This patch moves the definition for the PPC4xx NAND FLASH controller
(NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the
upcoming fix for the ECC byte ordering of the NDFC driver.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
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<pre>
This patch moves the definition for the PPC4xx NAND FLASH controller
(NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the
upcoming fix for the ECC byte ordering of the NDFC driver.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Blackfin: fix timer_init()/timer_reset()</title>
<updated>2009-05-19T08:57:33+00:00</updated>
<author>
<name>Graf Yang</name>
<email>graf.yang@analog.com</email>
</author>
<published>2009-05-19T08:40:08+00:00</published>
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<content type='text'>
The timer_init() function was not using the right csync instruction, nor
was it doing it right after disabling the core timer.

The timer_reset() function would reset the timestamp, but not the actual
timer, so there was a common edge case where get_timer() return a jump of
one timestamp (couple milliseconds) right after resetting.  This caused
many functions to improperly timeout right away.

Signed-off-by: Graf Yang &lt;graf.yang@analog.com&gt;
Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
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<pre>
The timer_init() function was not using the right csync instruction, nor
was it doing it right after disabling the core timer.

The timer_reset() function would reset the timestamp, but not the actual
timer, so there was a common edge case where get_timer() return a jump of
one timestamp (couple milliseconds) right after resetting.  This caused
many functions to improperly timeout right away.

Signed-off-by: Graf Yang &lt;graf.yang@analog.com&gt;
Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>MIPS: Implement ethernet halt for au1x00</title>
<updated>2009-05-16T00:20:03+00:00</updated>
<author>
<name>Thomas Lange</name>
<email>thomas@corelatus.se</email>
</author>
<published>2009-04-24T14:22:16+00:00</published>
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<id>87423d740b91329b8d1d0b73cafd6930993b558a</id>
<content type='text'>
Implement ethernet halt() by putting MAC0 in reset.
If we do not do this, we will get memory corruption
when ethernet frames are received during early OS boot.

Signed-off-by: Thomas Lange &lt;thomas@corelatus.se&gt;
Signed-off-by: Shinya Kuribayashi &lt;skuribay@pobox.com&gt;
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<pre>
Implement ethernet halt() by putting MAC0 in reset.
If we do not do this, we will get memory corruption
when ethernet frames are received during early OS boot.

Signed-off-by: Thomas Lange &lt;thomas@corelatus.se&gt;
Signed-off-by: Shinya Kuribayashi &lt;skuribay@pobox.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>74xx_7xx: Fix rounding problem in CPU frequency calculation</title>
<updated>2009-05-15T20:22:01+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2009-05-14T05:25:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c21f62d8483fbab44cd98d93ff2e9355a330d225'/>
<id>c21f62d8483fbab44cd98d93ff2e9355a330d225</id>
<content type='text'>
This patch fixes a problem in the CPU frequency calculation. Without it
a 798MHz CPU is displayed as 368.503 MHz. And with it it's 798 MHz.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
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<pre>
This patch fixes a problem in the CPU frequency calculation. Without it
a 798MHz CPU is displayed as 368.503 MHz. And with it it's 798 MHz.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Fix e-mail address of Gary Jennejohn.</title>
<updated>2009-05-15T20:11:59+00:00</updated>
<author>
<name>Detlev Zundel</name>
<email>dzu@denx.de</email>
</author>
<published>2009-05-13T08:54:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=792a09eb9d5d8c4f74b7e9f2e887316d511a4e80'/>
<id>792a09eb9d5d8c4f74b7e9f2e887316d511a4e80</id>
<content type='text'>
Signed-off-by: Detlev Zundel &lt;dzu@denx.de&gt;
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<pre>
Signed-off-by: Detlev Zundel &lt;dzu@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>MPC8260: fixup device tree by property instead of path</title>
<updated>2009-05-15T20:03:09+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2009-05-12T13:17:35+00:00</published>
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<id>fe6da4837308aa33d537ac3e7f36c2d66e3d9a36</id>
<content type='text'>
cpu/mpc8260/cpu.c used to use do_fixup_by_path_u32() to update the
clock frequencies in the device tree, using a CPU path
"/cpus/OF_CPU", with OF_CPU beind defined in the board config file.

However, this does not work when one board config file (here:
MPC8260ADS.h) is intended to be used for several diffrent CPUs and
therefor contains a generic definition like "cpu@0", as the device
trees that will then be loaded will contain specific names like
"PowerPC,8272@0".

We switch to using do_fixup_by_prop_u32() instead, so we can search
for device_type="cpu", as it is done in other architectures, too.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Tested-by: Heiko Schocher &lt;hs@denx.de&gt;
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<pre>
cpu/mpc8260/cpu.c used to use do_fixup_by_path_u32() to update the
clock frequencies in the device tree, using a CPU path
"/cpus/OF_CPU", with OF_CPU beind defined in the board config file.

However, this does not work when one board config file (here:
MPC8260ADS.h) is intended to be used for several diffrent CPUs and
therefor contains a generic definition like "cpu@0", as the device
trees that will then be loaded will contain specific names like
"PowerPC,8272@0".

We switch to using do_fixup_by_prop_u32() instead, so we can search
for device_type="cpu", as it is done in other architectures, too.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Tested-by: Heiko Schocher &lt;hs@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>AFEB9260 network fix</title>
<updated>2009-05-12T23:17:17+00:00</updated>
<author>
<name>Sergey Lapin</name>
<email>slapin@ossfans.org</email>
</author>
<published>2009-05-12T08:25:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c63254ef5628efe1c77cb2fdba20753f9666f55d'/>
<id>c63254ef5628efe1c77cb2fdba20753f9666f55d</id>
<content type='text'>
AFEB9260 uses PA10, PA11 for ETX2 and ETX3.
Also, due to extarnal pull-up on IRQ line, Micrel PHY ID is 1 after reset sequence,
not 0.

Signed-off-by: Sergey Lapin &lt;slapin@ossfans.org&gt;
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<pre>
AFEB9260 uses PA10, PA11 for ETX2 and ETX3.
Also, due to extarnal pull-up on IRQ line, Micrel PHY ID is 1 after reset sequence,
not 0.

Signed-off-by: Sergey Lapin &lt;slapin@ossfans.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Blackfin: avoid get_sclk() with early serial debug</title>
<updated>2009-05-06T12:47:27+00:00</updated>
<author>
<name>Mike Frysinger</name>
<email>vapier@gentoo.org</email>
</author>
<published>2009-04-25T03:54:19+00:00</published>
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When the clock functions were changed to use cached values (and thereby
avoiding expensive math functions), early serial debug broke because the
baud programming is called before external memory is available.

Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
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<pre>
When the clock functions were changed to use cached values (and thereby
avoiding expensive math functions), early serial debug broke because the
baud programming is called before external memory is available.

Signed-off-by: Mike Frysinger &lt;vapier@gentoo.org&gt;
</pre>
</div>
</content>
</entry>
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