u-boot.git/cpu, branch v2009.11.1

ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs

2010-01-23T16:53:22+00:00

On platforms where SPD EEPROM and another EEPROM have adjacent
I2C addresses SPD_EEPROM_ADDRESS should be defined as a single
element array, otherwise DDR2 setup code would fail with the
following error:

ERROR: Unknown DIMM detected in slot 1

However, fixing SPD_EEPROM_ADDRESS would result in another
error:

ERROR: DIMM's DDR1 and DDR2 type can not be mixed.

This happens because initdram() routine does not explicitly
initialize dimm_populated array. This patch fixes the problem.

Signed-off-by: Felix Radensky 
Signed-off-by: Stefan Roese

ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT

2010-01-23T16:53:11+00:00

Bootstrap options G and F are reported incorrectly (G instead
of F and vice versa). This patch fixes this.

Signed-off-by: Felix Radensky 
Signed-off-by: Stefan Roese

mpc83xx: boot time regression, move LCRR setup back to cpu_init_f

2009-12-09T17:40:52+00:00

Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.

This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.

E.G. on a 8347 board a bootup time increase of ~600ms has been observed:

   0.020 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.168 RS:    232
   0.172 I2C:   ready
   0.176 DRAM:  64 MB
   1.236 FLASH: 32 MB

Versus:

   0.016 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
   0.092 RS:    232
   0.092 I2C:   ready
   0.096 DRAM:  64 MB
   0.644 FLASH: 32 MB

So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.

Signed-off-by: Peter Korsgaard 
Signed-off-by: Kim Phillips

help: Correct syntax of nandecc help output.

2009-12-07T21:06:51+00:00

"nandecc" help output should not reproduce the command name, nor have
a trailing newline.

Signed-off-by: Robert P. J. Day

trab: fix warning: implicit declaration of function 'disable_vfd'

2009-12-07T20:50:18+00:00

Signed-off-by: Wolfgang Denk

mpc8260: move FDT memory node fixup into common CPU code.

2009-11-22T22:16:28+00:00

Signed-off-by: Marcel Ziswiler 
Tested-by: Heiko Schocher

ppc/85xx: Fix how we determine the number of CAM entries

2009-11-13T15:11:01+00:00

We were incorrectly use the max CAM size as the number of entries in
the array for setting up the addrmap.  We should be using the NENTRY
field which is the low 12-bits of TLB1CFG.

Signed-off-by: Kumar Gala

fsl-ddr: Fix the chip-select interleaving issue

2009-11-12T14:09:49+00:00

commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
introduced one new bug to chip-select interleaving.

Single DDR controller also can do the chip-select
interleaving if there is dual-rank or qual-rank DIMMs.

Signed-off-by: Dave Liu 
Signed-off-by: Kumar Gala

Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

2009-11-11T21:58:30+00:00

ppc4xx: 44x_spd_ddr2.c: Fix register macro ECCCR -> ECCES (SDRAM_ECCES)

2009-11-09T12:31:38+00:00

This error only appears when DEBUG is enabled in this driver. That's why
it went unnoticed till now.

Signed-off-by: Stefan Roese