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<title>u-boot.git/doc/README.arm-caches, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>doc: ARM: Use the right function name</title>
<updated>2015-01-14T16:37:39+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2015-01-14T14:36:34+00:00</published>
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Trivial fix.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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Trivial fix.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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</entry>
<entry>
<title>cache: add ALLOC_CACHE_ALIGN_BUFFER macro</title>
<updated>2011-10-25T07:23:10+00:00</updated>
<author>
<name>Anton staaf</name>
<email>robotboy@chromium.org</email>
</author>
<published>2011-10-12T13:55:59+00:00</published>
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<id>46a6d51c827a12723e7191128fb7aab42c8f5c09</id>
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This macro is used to allocate cache line size aligned stack
buffers for use with DMA hardware.

Signed-off-by: Anton Staaf &lt;robotboy@chromium.org&gt;
Cc: Lukasz Majewski &lt;l.majewski@samsung.com&gt;
Cc: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Cc: Mike Frysinger &lt;vapier@gentoo.org&gt;
Cc: Aneesh V &lt;aneesh@ti.com&gt;
Cc: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
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<pre>
This macro is used to allocate cache line size aligned stack
buffers for use with DMA hardware.

Signed-off-by: Anton Staaf &lt;robotboy@chromium.org&gt;
Cc: Lukasz Majewski &lt;l.majewski@samsung.com&gt;
Cc: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Cc: Mike Frysinger &lt;vapier@gentoo.org&gt;
Cc: Aneesh V &lt;aneesh@ti.com&gt;
Cc: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
</pre>
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</entry>
<entry>
<title>arm: do not force d-cache enable on all boards</title>
<updated>2011-09-04T09:36:16+00:00</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-08-16T04:33:05+00:00</published>
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c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.

Also add some documentation for cache usage in ARM.

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
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<pre>
c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.

Also add some documentation for cache usage in ARM.

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
</pre>
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