u-boot.git/doc/README.fsl-ddr, branch v2016.01

README.fsl-ddr typos and update to reflect hotkey

2013-01-30T17:25:13Z

Documentation fix to README.fsl-ddr to fix typos and to reflect use of 'd' hotkey to enter the FSL DDR debugger. Signed-off-by: James Yang Signed-off-by: Andy Fleming

Add copy command to FSL DDR interactive

2013-01-30T17:25:13Z

Add copy command which allows copying of DIMM/controller settings. This saves tedious retyping of parameters for each identical DIMM or controller. Signed-off-by: James Yang Signed-off-by: Andy Fleming

powerpc/mpc8xxx: Enable entering DDR debugging by key press

2013-01-30T17:25:12Z

Using environmental variable "ddr_interactive" to activate interactive DDR debugging seomtiems is not enough. For example, after updating SPD with a valid but wrong image, u-boot won't come up due to wrong DDR configuration. By enabling key press method, we can enter debug mode to have a chance to boot without using other tools to recover the board. CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the debug mode by key press, press key 'd' shortly after reset, like one would do to abort auto booting. It is fixed to lower case 'd' at this moment. Signed-off-by: York Sun Signed-off-by: Andy Fleming

powerpc/mpc8xxx: Add auto select bank interleaving mode

2012-10-22T19:31:30Z

Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or cs0_cs1 interleaving, or non-interleaving if not available. Fix the message of interleaving disabled if controller interleaving is enabled but DIMMs don't support it. Signed-off-by: York Sun Signed-off-by: Andy Fleming

powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving

2012-08-23T17:16:55Z

Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun Signed-off-by: Andy Fleming

doc: Fix some typos in different files

2012-03-27T11:31:37Z

adresses/addresses alernate/alternate asssuming/assuming calcualted/calculated enviroment/environment evalutation/evaluation falsh/flash labled/labeled paramaters/parameters Signed-off-by: Thomas Weber Acked-by: Anatolij Gustschin

powerpc/8xxx: Add support for interactive DDR programming interface

2011-10-09T22:57:53Z

Interactive DDR debugging provides a user interface to view and modify SPD, DIMM parameters, board options and DDR controller registers before DDR is initialized. With this feature, developers can fine-tune DDR for board bringup and other debugging without frequently having to reprogram the flash. To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header file and set an environment variable to activate it. Syntax: setenv ddr_interactive on After reset, U-boot prompts before initializing DDR controllers FSL DDR> The available commands are print print SPD and intermediate computed data reset reboot machine recompute reload SPD and options to default and recompute regs edit modify spd, parameter, or option compute recompute registers from current next_step to end next_step shows current next_step help this message go program the memory controller and continue with u-boot The first command should be "compute", which reads data from DIMM SPDs and board options, performs the calculation then stops before setting DDR controller. A user can use "print" and "edit" commands to view and modify anything. "Go" picks up from current step with any modification and compltes the calculation then enables the DDR controller to continue u-boot. "Recompute" does it over from fresh reading. Signed-off-by: York Sun Signed-off-by: Kumar Gala

powerpc/mpc8xxx: Add DDR2 to unified DDR driver

2011-09-30T00:01:06Z

DDR2 has different ODT table and values. Adding table according to Samsung application note. Fix additive latency calculation to avoid interger underflow. Also converted typedef dynamic_odt_t to struct dynamic_odt. Signed-off-by: York Sun Signed-off-by: Kumar Gala

Minor Coding Style Cleanup.

2011-02-02T21:36:10Z

Signed-off-by: Wolfgang Denk

mpc85xx: Enable unique mode registers and dynamic ODT for DDR3

2011-01-20T04:58:23Z

Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun Signed-off-by: Kumar Gala