u-boot.git/doc/README.fsl-esdhc, branch v2016.09Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/doc/README.fsl-esdhc?h=v2016.092015-05-04T16:25:19Zmmc: fsl_esdhc: Add adapter card type identification support2015-05-04T16:25:19ZYangbo Luyangbo.lu@freescale.com2015-04-22T05:57:00Zurn:sha1:5a8dbdc6b4b8b4b17c807c9bb23807cdc66f6feb
Add adapter card type identification support by reading
FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
define CONFIG_FSL_ESDHC_ADAPTER_IDENT.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
[York Sun: resolve conflicts in README.fsl-esdhc]
Reviewed-by: York Sun <yorksun@freescale.com>
mmc: fsl_esdhc: Add support to force VSELECT set2015-02-23T08:11:42ZOtavio Salvadorotavio@ossystems.com.br2015-02-17T12:42:44Zurn:sha1:ee0c538951018759eff4038db75e61b1cd040307
Some boards cannot do voltage negotiation but need to set the VSELECT
bit forcely to ensure it to work at 1.8V.
This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros2014-09-08T17:30:33ZWang Huanb18965@freescale.com2014-09-05T05:52:39Zurn:sha1:c82e9de400ee36038c76be67c5a6fb39c165ac1c
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang <alison.wang@freescale.com>