u-boot.git/doc/SPI, branch v2016.03 Unnamed repository; edit this file 'description' to name the repository. Use correct spelling of "U-Boot" 2016-02-06T11:00:59+00:00 Bin Meng bmeng.cn@gmail.com 2016-02-06T03:30:11+00:00 a187559e3d586891c917279044c5386d1b2adc6e Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> 
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
spi: altera: Add short note about EPCS/EPCQx1 2014-10-27T17:07:03+00:00 Marek Vasut marex@denx.de 2014-10-22T19:56:03+00:00 df155672ff262dd779ef12c04d9fc1911b778990 Add short documentation-alike note on how to use the Altera SPI driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V into doc/SPI/README.altera_spi Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> 
Add short documentation-alike note on how to use the Altera SPI
driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V
into doc/SPI/README.altera_spi

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
doc: SPI: Add qspi test details on AM43xx 2014-02-18T17:11:09+00:00 Sourav Poddar sourav.poddar@ti.com 2013-12-21T07:20:11+00:00 9ea09e20376abbca21760ed4ba87d6b5c4df465c This shows the log obtained while testing qspi on AM437x board. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
This shows the log obtained while testing qspi on AM437x  board.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
doc: SPI: Update status.txt 2014-01-12T16:10:23+00:00 Jagannadha Sutradharudu Teki jaganna@xilinx.com 2014-01-08T17:34:44+00:00 736ce857da3ecaa375130beede6a18000251ada8 Updated current SPI subsyetem status. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
Updated current SPI subsyetem status.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Add dual memories support - DUAL_PARALLEL 2014-01-12T16:10:22+00:00 Jagannadha Sutradharudu Teki jaganna@xilinx.com 2014-01-06T18:41:35+00:00 056fbc73d54df64adcb93c513cba708acb2683bd This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.

For more info - see doc/SPI/README.dual-flash

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Add dual memories support - DUAL_STACKED 2014-01-12T16:10:11+00:00 Jagannadha Sutradharudu Teki jaganna@xilinx.com 2014-01-12T16:10:11+00:00 f77f469117ab3184ac45683a50dc446265be28cc This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.

For more info - see doc/SPI/README.dual-flash

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: Add Faraday SPI controller support 2014-01-11T06:51:30+00:00 Kuo-Jung Su dantesu@faraday-tech.com 2013-12-20T07:24:30+00:00 66cb9eb1d6372b0d39b793688f80db5834d3ffab The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> CC: Tom Rini <trini@ti.com> 
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.

NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
CC: Tom Rini <trini@ti.com>
spi: Add support SH Quad SPI driver 2013-12-18T17:53:41+00:00 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com 2013-12-18T06:31:55+00:00 16f47c9c510a61ee91d6b9d02dd723522beff80f This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sandbox: spi: Add new SPI flash driver 2013-12-09T19:22:39+00:00 Mike Frysinger vapier@gentoo.org 2013-12-03T23:43:27+00:00 ffdb20bea16e00a326cc3d106f275e58bf302a0c This adds a SPI flash driver which simulates SPI flash clients. Currently supports the bare min that U-Boot requires: you can probe, read, erase, and write. Should be easy to extend to make it behave more exactly like a real SPI flash, but this is good enough to merge now. sjg@chromium.org added a README and tidied up code a little. Added a required map_sysmem() for sandbox. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org> 
This adds a SPI flash driver which simulates SPI flash clients.
Currently supports the bare min that U-Boot requires: you can
probe, read, erase, and write.  Should be easy to extend to make
it behave more exactly like a real SPI flash, but this is good
enough to merge now.

sjg@chromium.org added a README and tidied up code a little.
Added a required map_sysmem() for sandbox.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
doc: SPI: Update SPI status track 2013-10-07T14:05:10+00:00 Jagannadha Sutradharudu Teki jaganna@xilinx.com 2013-10-07T12:03:20+00:00 3cfcf774c270ecf6289203d88f859d1f91cb318e Updated SPI/status.txt, with memory_map and TODO. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
Updated SPI/status.txt, with memory_map and TODO.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>