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<title>riscv: Add AST2700 SoC initial platform support</title>
<updated>2024-09-11T12:35:03+00:00</updated>
<author>
<name>Chia-Wei Wang</name>
<email>chiawei_wang@aspeedtech.com</email>
</author>
<published>2024-09-10T09:39:16+00:00</published>
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AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.

This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
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<pre>
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.

This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.

Signed-off-by: Chia-Wei Wang &lt;chiawei_wang@aspeedtech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
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