u-boot.git/doc/board/socionext/developerbox.rst, branch master Unnamed repository; edit this file 'description' to name the repository. doc: fwu: make changes to reflect support for FWU metadata v2 2024-05-24T19:40:04+00:00 Sughosh Ganu sughosh.ganu@linaro.org 2024-03-22T10:57:31+00:00 7ef84369708993aeb523ae6a6abd5e5aab66196b The FWU Update Agent in U-Boot supports both versions of the FWU metadata. Make changes in the documentation to reflect this. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Tested-by: Michal Simek <michal.simek@amd.com> 
The FWU Update Agent in U-Boot supports both versions of the FWU
metadata. Make changes in the documentation to reflect this.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
board: developerbox: update flash rawwrite binary size 2023-10-31T17:08:10+00:00 Masahisa Kojima masahisa.kojima@linaro.org 2023-10-25T06:51:03+00:00 f50af7ebd72fde6a959f1f1e3f1ef371b9f2fce8 Current documentation limits the firmware size to 1.5MB. When the fTPM and StandaloneMM-based RPMB secure storage is enabled, firmware size is bigger than that size. Let's specify the A/B update bank size(4MB) for flash rawwrite parameter. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> 
Current documentation limits the firmware size to 1.5MB.
When the fTPM and StandaloneMM-based RPMB secure storage is
enabled, firmware size is bigger than that size.
Let's specify the A/B update bank size(4MB) for flash
rawwrite parameter.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
board: developerbox: update old NOR flash layout build instruction 2023-10-31T17:08:10+00:00 Masahisa Kojima masahisa.kojima@linaro.org 2023-10-25T06:51:02+00:00 1c9f9563f53739253a948b0f0e7eca8ec35ad5a9 v2023.07 is the last version supporting old NOR flash layout by default. The later versions of U-Boot, Developerbox is configured to enable A/B update and new NOR Flash layout by default. This commit updates the documentation to pin the U-Boot version for the old NOR flash layout. It is still useful for the user wants to replace the factory default EDK II firmware to U-Boot. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> 
v2023.07 is the last version supporting old NOR flash layout
by default. The later versions of U-Boot, Developerbox is
configured to enable A/B update and new NOR Flash layout
by default.
This commit updates the documentation to pin the U-Boot
version for the old NOR flash layout. It is still useful
for the user wants to replace the factory default EDK II
firmware to U-Boot.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
fwu: DeveloperBox: add support for FWU 2023-06-09T17:52:40+00:00 Jassi Brar jaswinder.singh@linaro.org 2023-05-31T05:29:56+00:00 6b403ca4dcf4c68e2792c4e8b28e03b3cfe5db45 Add code to support FWU_MULTI_BANK_UPDATE. The platform does not have gpt-partition storage for Banks and MetaData, rather it used SPI-NOR backed mtd regions for the purpose. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 
Add code to support FWU_MULTI_BANK_UPDATE.
The platform does not have gpt-partition storage for
Banks and MetaData, rather it used SPI-NOR backed
mtd regions for the purpose.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
board: synquacer: Add DeveloperBox 96boards EE support 2021-07-06T18:11:50+00:00 Masami Hiramatsu masami.hiramatsu@linaro.org 2021-06-04T09:45:10+00:00 5cd4a355e0f0addb718642b877939819b772936c Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> 
Add the DeveloperBox 96boards EE support. This board is also
known as Socionext SynQuacer E-Series. It contians one "SC2A11"
SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
3 PCIe slots (1 4x port and 2 1x ports which are expanded via
PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
MicroATX Form Factor.

For more information, see this page;
  https://www.96boards.org/product/developerbox/

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>