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<entry>
<title>Merge branch 'next'</title>
<updated>2026-04-06T18:16:57+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-04-06T18:16:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=93f84ee022a8401421cdaab84fe7d106d83fdb4a'/>
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</entry>
<entry>
<title>doc: board: ti: fix incorrect labels for boot switches</title>
<updated>2026-03-27T09:56:01+00:00</updated>
<author>
<name>Anshul Dalal</name>
<email>anshuld@ti.com</email>
</author>
<published>2026-03-13T09:41:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=22037a6ebb32f9b0fa2159dc6d66be7ca38468e6'/>
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The labels for the boot mode switches were incorreclty documented for
some TI boards, this patch fixes them as per the official user guides
linked below:

  AM62x     https://www.ti.com/lit/ug/spruj40e/spruj40e.pdf
  AM62dx    https://www.ti.com/lit/ug/sprujg2/sprujg2.pdf
  AM62ax    https://www.ti.com/lit/ug/spruj66b/spruj66b.pdf
  AM62px    https://www.ti.com/lit/ug/spruj40e/spruj40e.pdf
  AM6254atl https://www.ti.com/lit/ug/spruja1a/spruja1a.pdf

Signed-off-by: Anshul Dalal &lt;anshuld@ti.com&gt;
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<pre>
The labels for the boot mode switches were incorreclty documented for
some TI boards, this patch fixes them as per the official user guides
linked below:

  AM62x     https://www.ti.com/lit/ug/spruj40e/spruj40e.pdf
  AM62dx    https://www.ti.com/lit/ug/sprujg2/sprujg2.pdf
  AM62ax    https://www.ti.com/lit/ug/spruj66b/spruj66b.pdf
  AM62px    https://www.ti.com/lit/ug/spruj40e/spruj40e.pdf
  AM6254atl https://www.ti.com/lit/ug/spruja1a/spruja1a.pdf

Signed-off-by: Anshul Dalal &lt;anshuld@ti.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>doc: board: fix OPTEE args for TI SoCs</title>
<updated>2026-03-27T09:55:46+00:00</updated>
<author>
<name>Anshul Dalal</name>
<email>anshuld@ti.com</email>
</author>
<published>2026-03-12T09:32:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=155cd085616c2f3c274c4baf45a28723d08e6f6d'/>
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CFG_WITH_SOFTWARE_PRNG=y was added as an OPTEE argument to workaround
some bugs related to TRNG which have been fixed now[1]. Therefore this
patch drops the redundant argument from the documentation.

[1]: https://github.com/OP-TEE/optee_os/commit/e313f4765fd0478bb66985827441411793433773

Signed-off-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Acked-by: Francesco Dolcini &lt;francesco.dolcini@toradex.com&gt; # Toradex Verdin AM62
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CFG_WITH_SOFTWARE_PRNG=y was added as an OPTEE argument to workaround
some bugs related to TRNG which have been fixed now[1]. Therefore this
patch drops the redundant argument from the documentation.

[1]: https://github.com/OP-TEE/optee_os/commit/e313f4765fd0478bb66985827441411793433773

Signed-off-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Acked-by: Francesco Dolcini &lt;francesco.dolcini@toradex.com&gt; # Toradex Verdin AM62
</pre>
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</content>
</entry>
<entry>
<title>Merge patch series "Add PCIe Boot support for TI J784S4 SoC"</title>
<updated>2026-03-16T14:24:18+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-03-16T14:24:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=841856ed9675b26ec517fdd00b5cc0aef8db508e'/>
<id>841856ed9675b26ec517fdd00b5cc0aef8db508e</id>
<content type='text'>
Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt; says:

This series adds PCIe endpoint boot support for the TI J784S4 SoC.
Series is based on commit f9ffeec4bdc ("board: toradex: Make A53 get RAM
size from DT in K3 boards") of the master branch of U-Boot.

PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers
bootloaders to another J784S4-EVM configured for PCIe Boot):
https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a

Link: https://lore.kernel.org/r/20260216102858.2745657-1-s-vadapalli@ti.com
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<pre>
Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt; says:

This series adds PCIe endpoint boot support for the TI J784S4 SoC.
Series is based on commit f9ffeec4bdc ("board: toradex: Make A53 get RAM
size from DT in K3 boards") of the master branch of U-Boot.

PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers
bootloaders to another J784S4-EVM configured for PCIe Boot):
https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a

Link: https://lore.kernel.org/r/20260216102858.2745657-1-s-vadapalli@ti.com
</pre>
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</content>
</entry>
<entry>
<title>docs: board: ti: j784s4_evm: Add PCIe boot documentation</title>
<updated>2026-03-16T14:24:04+00:00</updated>
<author>
<name>Hrushikesh Salunke</name>
<email>h-salunke@ti.com</email>
</author>
<published>2026-02-16T10:28:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6230a595a733e381ecdbe35199d255f3d5801955'/>
<id>6230a595a733e381ecdbe35199d255f3d5801955</id>
<content type='text'>
Add PCIe boot documentation for J784S4-EVM including boot mode switch
settings, hardware setup requirements, endpoint configuration details
and step-by-step boot procedure.

Signed-off-by: Hrushikesh Salunke &lt;h-salunke@ti.com&gt;
[s-vadapalli@ti.com: simplified and documented the pcie_boot_util program]
Co-developed-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
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<pre>
Add PCIe boot documentation for J784S4-EVM including boot mode switch
settings, hardware setup requirements, endpoint configuration details
and step-by-step boot procedure.

Signed-off-by: Hrushikesh Salunke &lt;h-salunke@ti.com&gt;
[s-vadapalli@ti.com: simplified and documented the pcie_boot_util program]
Co-developed-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Reviewed-by: Udit Kumar &lt;u-kumar1@ti.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Merge patch series "k3_*: Add config fragments for inline ECC and BIST"</title>
<updated>2026-03-13T22:17:15+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-03-13T20:59:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1ad466eeae393b14fd70e5c414b37ca64413bf2b'/>
<id>1ad466eeae393b14fd70e5c414b37ca64413bf2b</id>
<content type='text'>
Neha Malcom Francis &lt;n-francis@ti.com&gt; says:

Typically we do not enable these configs by default but would still like to
have the option to start building them in our default build flow for
testing. Also there is the added advantage of users being able to see what
is needed in case they choose to enable these features.

Link: https://lore.kernel.org/r/20260226122508.2269682-1-n-francis@ti.com
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<pre>
Neha Malcom Francis &lt;n-francis@ti.com&gt; says:

Typically we do not enable these configs by default but would still like to
have the option to start building them in our default build flow for
testing. Also there is the added advantage of users being able to see what
is needed in case they choose to enable these features.

Link: https://lore.kernel.org/r/20260226122508.2269682-1-n-francis@ti.com
</pre>
</div>
</content>
</entry>
<entry>
<title>doc: board: ti: Add support for config fragment builds</title>
<updated>2026-03-13T22:17:15+00:00</updated>
<author>
<name>Neha Malcom Francis</name>
<email>n-francis@ti.com</email>
</author>
<published>2026-02-26T12:25:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=112bb951242b01762d57569b8d0dd406ffe9cc48'/>
<id>112bb951242b01762d57569b8d0dd406ffe9cc48</id>
<content type='text'>
Add sections dedicated to explaining how BIST and inline ECC can be
enabled via the config fragments.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</content>
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<pre>
Add sections dedicated to explaining how BIST and inline ECC can be
enabled via the config fragments.

Signed-off-by: Neha Malcom Francis &lt;n-francis@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>doc: am335x: document use of CONFIG_SPL_AM33XX_MMCSD_MULTIPLE</title>
<updated>2026-02-10T21:54:04+00:00</updated>
<author>
<name>Rasmus Villemoes</name>
<email>ravi@prevas.dk</email>
</author>
<published>2026-01-29T10:54:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a672456d4b2bd216dcfe9d09fb5fbce2b013735a'/>
<id>a672456d4b2bd216dcfe9d09fb5fbce2b013735a</id>
<content type='text'>
Document how one can use the CONFIG_SPL_AM33XX_MMCSD_MULTIPLE option
to implement a scheme for failsafe updating of the whole bootloader on
the am335x.

Signed-off-by: Rasmus Villemoes &lt;ravi@prevas.dk&gt;
</content>
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<pre>
Document how one can use the CONFIG_SPL_AM33XX_MMCSD_MULTIPLE option
to implement a scheme for failsafe updating of the whole bootloader on
the am335x.

Signed-off-by: Rasmus Villemoes &lt;ravi@prevas.dk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>doc: board: ti: Add AM62D documentation</title>
<updated>2026-01-19T09:31:21+00:00</updated>
<author>
<name>Paresh Bhagat</name>
<email>p-bhagat@ti.com</email>
</author>
<published>2026-01-17T03:33:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8e16fbfd14b48d428062a0eec47912424963d01e'/>
<id>8e16fbfd14b48d428062a0eec47912424963d01e</id>
<content type='text'>
Add info of boot flow and build steps for AM62Dx EVM.

Signed-off-by: Paresh Bhagat &lt;p-bhagat@ti.com&gt;
</content>
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<pre>
Add info of boot flow and build steps for AM62Dx EVM.

Signed-off-by: Paresh Bhagat &lt;p-bhagat@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Update links to doc/develop/falcon.rst</title>
<updated>2026-01-19T09:31:21+00:00</updated>
<author>
<name>J. Neuschäfer</name>
<email>j.ne@posteo.net</email>
</author>
<published>2026-01-01T14:17:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba8ca7965b506a7c759da7907148609df6d9e715'/>
<id>ba8ca7965b506a7c759da7907148609df6d9e715</id>
<content type='text'>
README.falcon was converted to ReST/HTML in 2023.

Signed-off-by: J. Neuschäfer &lt;j.ne@posteo.net&gt;
Reviewed-by: Mattijs Korpershoek &lt;mkorpershoek@kernel.org&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
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<pre>
README.falcon was converted to ReST/HTML in 2023.

Signed-off-by: J. Neuschäfer &lt;j.ne@posteo.net&gt;
Reviewed-by: Mattijs Korpershoek &lt;mkorpershoek@kernel.org&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</pre>
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