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<title>u-boot.git/doc/board, branch v2023.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/doc/board?h=v2023.04</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/doc/board?h=v2023.04'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2023-03-27T01:38:44Z</updated>
<entry>
<title>x86: minnowmax: Fix up adjustment of CONFIG_TEXT_BASE</title>
<updated>2023-03-27T01:38:44Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-03-14T23:59:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f1d87db49bdc1cc97e0ee5636b20f1a99c4fcaf2'/>
<id>urn:sha1:f1d87db49bdc1cc97e0ee5636b20f1a99c4fcaf2</id>
<content type='text'>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.

Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.

Add documentation on how to make this change safely.

Fixes: 66e2c665f3b6 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>board: rockchip: add Radxa ROCK5B Rk3588 board</title>
<updated>2023-02-28T10:07:29Z</updated>
<author>
<name>Eugen Hristev</name>
<email>eugen.hristev@collabora.com</email>
</author>
<published>2023-02-22T09:05:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3bf8e40807632071769f1dfa401662c5336802c9'/>
<id>urn:sha1:3bf8e40807632071769f1dfa401662c5336802c9</id>
<content type='text'>
ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa.

There are tree variants depending on the DRAM size : 4G, 8G and 16G.

Specification:

    Rockchip Rk3588 SoC
    4x ARM Cortex-A76, 4x ARM Cortex-A55
    4/8/16GB memory LPDDR4x
    Mali G610MC4 GPU
    MIPI CSI 2 multiple lanes connector
    eMMC module connector
    uSD slot (up to 128GB)
    2x USB 2.0, 2x USB 3.0
    2x HDMI output, 1x HDMI input
    Ethernet port
    40-pin IO header including UART, SPI, I2C and 5V DC power in
    USB PD over USB Type-C
    Size: 85mm x 54mm

Kernel commits:
a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board")
6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b")

Signed-off-by: Eugen Hristev &lt;eugen.hristev@collabora.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>board: rockchip: Add Edgeble Neural Compute Module 6</title>
<updated>2023-02-28T10:07:28Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2023-01-30T14:57:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=15b2d1fb727b5e09ec95a0c613f8fac5752f1a76'/>
<id>urn:sha1:15b2d1fb727b5e09ec95a0c613f8fac5752f1a76</id>
<content type='text'>
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.

General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC

On module WiFi6/BT5 is available in the following Neu6 variants.

Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.

IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.

Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.

Boot log for the record,

DDR Version V1.08 20220617
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
Manufacturer ID:0x6
CH0 RX Vref:31.7%, TX Vref:21.8%,21.8%
CH1 RX Vref:30.7%, TX Vref:22.8%,23.8%
CH2 RX Vref:30.7%, TX Vref:22.8%,22.8%
CH3 RX Vref:30.7%, TX Vref:21.8%,21.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out

U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Trying to boot from MMC1
INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-391-g856309329:derrick.huang
NOTICE:  BL31: Built : 14:15:50, Jul 18 2022
INFO:    ext 32k is not valid
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    system boots from cpu-hwid-0
INFO:    idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO:    dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO:    dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO:    dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO:    dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO:    BL31: Initialising Exception Handling Framework
INFO:    BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR:   Error initializing runtime service opteed_fast
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xa00000
INFO:    SPSR = 0x3c9

U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)

Model: Edgeble Neu6A IO Board
DRAM:  7.5 GiB (effective 3.7 GiB)
Core:  71 devices, 15 uclasses, devicetree: separate
MMC:   mmc@fe2c0000: 0
Loading Environment from nowhere... OK
In:    serial@feb50000
Out:   serial@feb50000
Err:   serial@feb50000
Model: Edgeble Neu6A IO Board
Net:   No ethernet found.
Hit any key to stop autoboot:  0
=&gt;

Add support for Edgeble Neu6 Model A IO Board.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>evb-rk3568: Update MAINTAINERS and documentation</title>
<updated>2023-02-28T10:07:27Z</updated>
<author>
<name>Chris Morgan</name>
<email>macromorgan@hotmail.com</email>
</author>
<published>2023-02-13T22:27:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9b78a98ee5e7e349f0f7e7c216d89ce7f8835a0f'/>
<id>urn:sha1:9b78a98ee5e7e349f0f7e7c216d89ce7f8835a0f</id>
<content type='text'>
Update the MAINTAINERS file to include the devicetree for the
rk3568-evb1-v10 board.

Also update Rockchip board docs to include information on building
RK3568 based devices.

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: Use an external TPL binary on RK3568</title>
<updated>2023-02-28T10:07:26Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2023-02-25T19:01:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4773e9d5ed4c12e02759f1d732bb66006139037a'/>
<id>urn:sha1:4773e9d5ed4c12e02759f1d732bb66006139037a</id>
<content type='text'>
Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then
jumps to U-Boot SPL to continue the normal boot flow.

However, there is no support to initialize DRAM on RK35xx SoCs using
U-Boot TPL and instead an external TPL binary must be used to generate a
bootable u-boot-rockchip.bin image.

Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should
be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a
bootable u-boot-rockchip.bin image for RK3568.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Tested-by: Eugen Hristev &lt;eugen.hristev@collabora.com&gt;
</content>
</entry>
<entry>
<title>board: gateworks: venice: move README to RST</title>
<updated>2023-02-19T20:15:15Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2023-02-13T17:44:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=98382917d7924435f354567def119e55e84e2ba3'/>
<id>urn:sha1:98382917d7924435f354567def119e55e84e2ba3</id>
<content type='text'>
Move board/gateworks/venice/README to RST documentation.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
</entry>
<entry>
<title>doc: board: bcm7xxx: Convert to reStructuredText format</title>
<updated>2023-02-19T20:15:15Z</updated>
<author>
<name>Thomas Fitzsimmons</name>
<email>fitzsim@fitzsim.org</email>
</author>
<published>2023-02-13T16:21:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34a1fee7565e46795c8f8404a0be68e928c1e63c'/>
<id>urn:sha1:34a1fee7565e46795c8f8404a0be68e928c1e63c</id>
<content type='text'>
Convert the documentation for the Broadcom BCM7445 and BCM7260 boards
to reStructuredText format and add the new filename to
doc/board/broadcom/index.rst.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
</entry>
<entry>
<title>riscv: Rename Andes cpu and board names</title>
<updated>2023-02-17T11:07:48Z</updated>
<author>
<name>Leo Yu-Chi Liang</name>
<email>ycliang@andestech.com</email>
</author>
<published>2023-02-14T12:42:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8900e2bbecd021b16eee7c344cd6ca0e1ee901f3'/>
<id>urn:sha1:8900e2bbecd021b16eee7c344cd6ca0e1ee901f3</id>
<content type='text'>
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.

Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-20230201' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx</title>
<updated>2023-02-01T14:30:52Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-02-01T14:30:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3592a61fa8b4b55c0fab9a75bfb9ac3c73fdcbc0'/>
<id>urn:sha1:3592a61fa8b4b55c0fab9a75bfb9ac3c73fdcbc0</id>
<content type='text'>
For 2023.04
-----------

- several conversion to DM_SERIAL and DM_I2C
- fixes for Toradex boards
- PSCI

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-amlogic-20230131' of https://source.denx.de/u-boot/custodians/u-boot-amlogic</title>
<updated>2023-01-31T15:15:39Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-01-31T15:15:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=095d909cf101356cc36a12ec447a862b2477842d'/>
<id>urn:sha1:095d909cf101356cc36a12ec447a862b2477842d</id>
<content type='text'>
- jethub j100: add rescue boot from microSD
- move meson sm command to cmd/meson and add efusedump sub-command
- switch dwc2 otg to DM for G12A, GXL &amp; AXG
- Add new boards:
 - Odroid Go Ultra
 - Odroid-N2L
</content>
</entry>
</feed>
