u-boot.git/doc/device-tree-bindings/clock, branch v2017.07 Unnamed repository; edit this file 'description' to name the repository. Merge git://git.denx.de/u-boot-rockchip 2017-03-17T18:15:17+00:00 Tom Rini trini@konsulko.com 2017-03-17T13:11:12+00:00 f9515756b6d76cde99b385dda905dfb20d31ea48 This includes support for rk3188 from Heiko Stübner and and rk3328 from Kever Yang. Also included is SPL support for rk3399 and a fix for rk3288 to get it booting again (spl_early_init()). 
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang.  Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
clk: stm32f7: add clock driver for stm32f7 family 2017-03-17T18:15:12+00:00 Vikas Manocha vikas.manocha@st.com 2017-02-12T18:25:45+00:00 712f99a5ddc404f8c6eac481cfe19f82ca2ecb4f add basic clock driver support for stm32f7 to enable clocks required by the peripherals. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
rockchip: arm64: rk3399: add ddr controller driver 2017-03-16T22:03:45+00:00 Kever Yang kever.yang@rock-chips.com 2017-02-22T08:56:35+00:00 fa437430ad9861886f5766151757a99de647d086 RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from coreboot, support 4GB lpddr3 in this version. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org> 
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Added rockchip: tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
drivers: clk: Add clock driver for Microchip PIC32 Microcontroller. 2016-02-01T21:14:00+00:00 Purna Chandra Mandal purna.mandal@microchip.com 2016-01-28T10:00:11+00:00 a0e7908326b9dcde4c27dbbcbc52ccbf9e009255 PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
rockchip: Bring in RK3288 device tree file includes and bindings 2015-09-03T03:28:23+00:00 Simon Glass sjg@chromium.org 2015-08-30T22:55:20+00:00 344c837686b4268882ee4942f2a1e5e5716c7383 Bring in required device tree files from Linux. Since mainline Linux is somewhat behind, use the files from the Chromium tree. We can re-sync once further code is acccepted upstream. Signed-off-by: Simon Glass <sjg@chromium.org> 
Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.

Signed-off-by: Simon Glass <sjg@chromium.org>
tegra: fdt: Add clock bindings 2012-03-29T06:12:48+00:00 Simon Glass sjg@chromium.org 2012-02-27T10:52:43+00:00 1f1a02123cc1643517498e93497a67dfe8824bd7 This adds a basic binding for the oscillator and peripheral clocks. The second cell is the clock number, defined as the bit number within the clock enable register if the peripheral clock. This uses the RFC clock bindings from Grant Likely so may change later: https://lkml.org/lkml/2011/12/12/498 It is taken from Stephen Warren's patch here: http://patchwork.ozlabs.org/patch/141359/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 
This adds a basic binding for the oscillator and peripheral clocks. The
second cell is the clock number, defined as the bit number within the clock
enable register if the peripheral clock.

This uses the RFC clock bindings from Grant Likely so may change later:

https://lkml.org/lkml/2011/12/12/498

It is taken from Stephen Warren's patch here:

http://patchwork.ozlabs.org/patch/141359/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>