u-boot.git/doc/device-tree-bindings/firmware, branch master Unnamed repository; edit this file 'description' to name the repository. dt/bindings: fwu-mdata-mtd: drop changes outside FWU 2023-06-09T17:24:10+00:00 Jassi Brar jaswinder.singh@linaro.org 2023-03-06T23:18:14+00:00 56b481c42879ae171c6272f92ff5db7c767929af Any requirement of FWU should not require changes to bindings of other subsystems. For example, for mtd-backed storage we can do without requiring 'fixed-partitions' children to also carry 'uuid', a property which is non-standard and not in the bindings. There exists no code yet, so we can change the fwu-mtd bindings to contain all properties within the fwu-mdata node. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-by: Sughosh Ganu <sughosh.ganu@linaro.org> 
Any requirement of FWU should not require changes to bindings
of other subsystems. For example, for mtd-backed storage we
can do without requiring 'fixed-partitions' children to also
carry 'uuid', a property which is non-standard and not in the
bindings.

 There exists no code yet, so we can change the fwu-mtd bindings
to contain all properties within the fwu-mdata node.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
efi_loader: get lowest supported version from device tree 2023-06-08T07:20:36+00:00 Masahisa Kojima masahisa.kojima@linaro.org 2023-06-07T05:41:54+00:00 25dc7d5aedfef310a7e49b37e2556dc84b79cb00 This commit gets the lowest supported version from device tree, then fills the lowest supported version in FMP->GetImageInfo(). Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> 
This commit gets the lowest supported version from device tree,
then fills the lowest supported version in FMP->GetImageInfo().

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
dt/bindings: Add bindings for GPT based FWU Metadata storage device 2022-10-31T18:47:32+00:00 Sughosh Ganu sughosh.ganu@linaro.org 2022-10-21T12:45:54+00:00 73981390dfea84b2861d285b2d1b2fd33a84b665 Add bindings needed for accessing the FWU metadata partitions. These include the compatible string which point to the access method and the actual device which stores the FWU metadata. The current patch adds basic bindings needed for accessing the metadata structure on GPT partitioned block devices. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> 
Add bindings needed for accessing the FWU metadata partitions. These
include the compatible string which point to the access method and the
actual device which stores the FWU metadata.

The current patch adds basic bindings needed for accessing the
metadata structure on GPT partitioned block devices.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
dt/bindings: Add bindings for FWU Metadata mtd storage 2022-09-01T05:42:28+00:00 Sughosh Ganu sughosh.ganu@linaro.org 2022-07-22T17:43:15+00:00 2ac4c98ad3552609fdf04d874e60ef2c073c4689 Add bindings needed for accessing the FWU metadata regions. These include the compatible string which point to the access method, the actual device which stores the FWU metadata and the offsets for both metadata regions. The current patch adds basic bindings needed for accessing the metadata structure on non-GPT mtd regions. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> 
Add bindings needed for accessing the FWU metadata regions.
These include the compatible string which point to the access
method, the actual device which stores the FWU metadata and
the offsets for both metadata regions.

The current patch adds basic bindings needed for accessing the
metadata structure on non-GPT mtd regions.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
WS cleanup: remove excessive empty lines 2021-09-30T12:08:56+00:00 Wolfgang Denk wd@denx.de 2021-09-27T15:42:37+00:00 c72231d2729cea8b683ef05d94c986ced36755b3 Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
firmware: ti_sci: Add support for Resoure Management at R5 SPL stage. 2021-06-11T13:48:52+00:00 Vignesh Raghavendra vigneshr@ti.com 2021-06-07T14:17:49+00:00 5d5a699855a704646b10c4f04dc9ce0650ceace3 On J721e and J7200, MCU R5 core (boot master) itself would run Device Manager (DM) Firmware and interact with TI Foundational Security (TIFS) firmware to enable DMA and such other Resource Management (RM) services. So, during R5 SPL stage there is no such RM service available and ti_sci driver will have to directly interact with TIFS using DM to DMSC channels to request RM resources. Therefore add DT binding and driver for the same. This driver will handle Resource Management services at R5 SPL stage. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-4-vigneshr@ti.com 
On J721e and J7200, MCU R5 core (boot master) itself would run Device
Manager (DM) Firmware and interact with TI Foundational Security (TIFS)
firmware to enable DMA and such other Resource Management (RM) services.
So, during R5 SPL stage there is no such RM service available and ti_sci
driver will have to directly interact with TIFS using DM to DMSC
channels to request RM resources.

Therefore add DT binding and driver for the same. This driver will
handle Resource Management services at R5 SPL stage.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-4-vigneshr@ti.com
dt/bindings: add bindings for optee 2018-10-07T14:47:38+00:00 Jens Wiklander jens.wiklander@linaro.org 2018-09-25T14:40:10+00:00 53b6aac7b1a1fa057403a619e3716b7f8baed211 Sync with c8bfafb15944 ("dt/bindings: add bindings for optee") from Linux kernel. Introduces linaro prefix and adds bindings for ARM TrustZone based OP-TEE implementation. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> 
Sync with c8bfafb15944 ("dt/bindings: add bindings for optee")
from Linux kernel.

Introduces linaro prefix and adds bindings for ARM TrustZone based OP-TEE
implementation.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
firmware: Add basic support for TI System Control Interface (TI SCI) protocol 2018-09-11T12:32:55+00:00 Lokesh Vutla lokeshvutla@ti.com 2018-08-27T10:27:32+00:00 32cd25128bd8497db7a239e1eb9c338398fb42bc Texas Instrument's System Control Interface (TI SCI) message protocol is used in Texas Instrument's System on Chip (SoC) such as those in the K3 family AM654 SoC to communicate between various compute processors with a central system controller entity. The TI SCI message protocol provides support for management of various hardware entities within the SoC. Add support driver to allow communication with system controller entity within the SoC using the mailbox client. This is mostly derived from the TI SCI driver in Linux located at drivers/firmware/ti_sci.c. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> 
Texas Instrument's System Control Interface (TI SCI) message protocol is
used in Texas Instrument's System on Chip (SoC) such as those in the K3
family AM654 SoC to communicate between various compute processors with
a central system controller entity.

The TI SCI message protocol provides support for management of various
hardware entities within the SoC. Add support driver to allow
communication with system controller entity within the SoC using the
mailbox client.

This is mostly derived from the TI SCI driver in Linux located at
drivers/firmware/ti_sci.c.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
dt-bindings: allow child nodes inside the Tegra BPMP 2016-08-04T20:36:59+00:00 Stephen Warren swarren@nvidia.com 2016-07-29T19:15:00+00:00 390ae57c762b65d40d39355858960f13f06cfcd4 The BPMP implements some services which must be represented by separate nodes. For example, it can provide access to certain I2C controllers, and the I2C bindings represent each I2C controller as a device tree node. Update the binding to describe how the BPMP supports this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> 
The BPMP implements some services which must be represented by separate
nodes. For example, it can provide access to certain I2C controllers, and
the I2C bindings represent each I2C controller as a device tree node.
Update the binding to describe how the BPMP supports this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
ARM: tegra: add BPMP DT bindings 2016-08-04T20:36:58+00:00 Stephen Warren swarren@nvidia.com 2016-07-27T21:24:50+00:00 7b9cb4940575f3b2d368d56ca06d3c0330af4c4b The Tegra BPMP (Boot and Power Management Processor) is a separate auxiliary CPU embedded into Tegra to perform power management work, and controls related features such as clocks, resets, power domains, PMIC I2C bus, etc. These bindings dictate how to represent the BPMP in device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. These bindings dictate how to represent the BPMP in device tree.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>