<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/doc/device-tree-bindings/memory-controller, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>dm: doc: Update device tree binding docs for new schema</title>
<updated>2023-02-14T16:43:27+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-02-13T15:56:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c8ef3eed61796293b744d33739fe4f601af40a17'/>
<id>c8ef3eed61796293b744d33739fe4f601af40a17</id>
<content type='text'>
Now that Linux has accepted these tags, move U-Boot over to use them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Now that Linux has accepted these tags, move U-Boot over to use them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ram: k3-ddrss: Allow use of dt provided initial frequency</title>
<updated>2022-04-20T15:14:39+00:00</updated>
<author>
<name>Dave Gerlach</name>
<email>d-gerlach@ti.com</email>
</author>
<published>2022-04-08T21:46:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=270f7fd25b3d1e825d3364eee652c3ccc9d5aae4'/>
<id>270f7fd25b3d1e825d3364eee652c3ccc9d5aae4</id>
<content type='text'>
Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR
frequency that is set for lpddr4 before initialization of the
controller. Make this optional and continue to use PLL bypass frequency
as is done currently if ti,ddr-freq0 is not provided.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR
frequency that is set for lpddr4 before initialization of the
controller. Make this optional and continue to use PLL bypass frequency
as is done currently if ti,ddr-freq0 is not provided.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: memory-controller: Add information about ECC bindings</title>
<updated>2022-04-04T23:02:04+00:00</updated>
<author>
<name>Dave Gerlach</name>
<email>d-gerlach@ti.com</email>
</author>
<published>2022-03-17T17:03:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7b8a96e57e1db60f742184822a7d8dc508605f1f'/>
<id>7b8a96e57e1db60f742184822a7d8dc508605f1f</id>
<content type='text'>
Add DT binding documentation for enabling ECC in the DDR sub system present
on AM64 device.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add DT binding documentation for enabling ECC in the DDR sub system present
on AM64 device.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>WS cleanup: remove SPACE(s) followed by TAB</title>
<updated>2021-09-30T13:08:16+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2021-09-27T15:42:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0cf207ec01cbacae47585fcc26591dd2296507d6'/>
<id>0cf207ec01cbacae47585fcc26591dd2296507d6</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: memory-controller: Add K3 AM64 DDRSS compatible</title>
<updated>2021-05-12T11:00:52+00:00</updated>
<author>
<name>Dave Gerlach</name>
<email>d-gerlach@ti.com</email>
</author>
<published>2021-05-11T15:21:59+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=760b7488f531a627ce6ed0a1bddc7a8522fbf612'/>
<id>760b7488f531a627ce6ed0a1bddc7a8522fbf612</id>
<content type='text'>
Update the k3-ddrss DT binding document to include compatible
for k3,am64-ddrss.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Update the k3-ddrss DT binding document to include compatible
for k3,am64-ddrss.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: memory-controller: Introduce J721E DDRSS bindings</title>
<updated>2019-10-25T21:33:21+00:00</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2019-10-07T13:56:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ffb6b8e540f9badfeba188663c96aa4980f41612'/>
<id>ffb6b8e540f9badfeba188663c96aa4980f41612</id>
<content type='text'>
Add DT binding documentation for DDR sub system present on J721E device.

Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add DT binding documentation for DDR sub system present on J721E device.

Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
