u-boot.git/doc/device-tree-bindings/misc/intel-lpc.txt, branch master Unnamed repository; edit this file 'description' to name the repository. x86: ivybridge: Add additional LPC init 2014-11-25T13:34:01+00:00 Simon Glass sjg@chromium.org 2014-11-15T01:18:35+00:00 72cd085aaed511abf1ece0b406b79b90d26826af Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org> 
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: ivybridge: Add early LPC init so that serial works 2014-11-21T06:34:12+00:00 Simon Glass sjg@chromium.org 2014-11-13T05:42:15+00:00 2b6051541b562b72d2cf784376a84552da18318d The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> 
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>