u-boot.git/doc/device-tree-bindings/net/phy, branch master Unnamed repository; edit this file 'description' to name the repository. phy: adin: add driver for Analog Devices ADIN1300 PHY 2022-04-10T05:44:13+00:00 Nate Drude nate.d@variscite.com 2022-04-08T16:28:14+00:00 d79f1a85697e3af24a97728f6e4f16635bdc8290 The current implementation configures RGMII using device tree phy-mode property and then calls genphy_config adin_config_rgmii_mode is derived from: https://github.com/varigit/linux-imx/blob/lf-5.10.y_var04/drivers/net/phy/adin.c#L218-L262 Signed-off-by: Nate Drude <nate.d@variscite.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> 
The current implementation configures RGMII using device tree phy-mode
property and then calls genphy_config

adin_config_rgmii_mode is derived from:
https://github.com/varigit/linux-imx/blob/lf-5.10.y_var04/drivers/net/phy/adin.c#L218-L262

Signed-off-by: Nate Drude <nate.d@variscite.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
phy: atheros: Fix the "qca,clk-out-frequency" example 2020-06-23T18:43:23+00:00 Fabio Estevam festevam@gmail.com 2020-06-17T18:07:04+00:00 ccbda9e68093b0c6019b95596366faec2b19442d The correct name for the property is "qca,clk-out-frequency", so fix it accordingly. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> 
The correct name for the property is "qca,clk-out-frequency", so fix
it accordingly.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Michael Walle <michael@walle.cc>
phy: atheros: add device tree bindings and config 2020-05-07T15:05:00+00:00 Michael Walle michael@walle.cc 2020-05-06T22:11:57+00:00 fe6293a8095998affd5e46e7968485fcc332e0fa Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 
Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.

By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output.

Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>