u-boot.git/doc/device-tree-bindings/ram, branch master Unnamed repository; edit this file 'description' to name the repository. dm: doc: Update device tree binding docs for new schema 2023-02-14T16:43:27+00:00 Simon Glass sjg@chromium.org 2023-02-13T15:56:35+00:00 c8ef3eed61796293b744d33739fe4f601af40a17 Now that Linux has accepted these tags, move U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org> 
Now that Linux has accepted these tags, move U-Boot over to use them.

Signed-off-by: Simon Glass <sjg@chromium.org>
doc: Remove duplicated documentation directory 2019-06-20T14:57:08+00:00 Breno Matheus Lima breno.lima@nxp.com 2019-06-05T18:18:30+00:00 656d8da9d2862afd293ae678d37a486d34b76ca2 Commit ad7061ed742e ("doc: Move device tree bindings documentation to doc/device-tree-bindings") moved all device tree binding documentation to doc/device-tree-bindings directory. The current U-Boot project still have two documentation directories: - doc/ - Documentation/ Move all documentation and sphinx files to doc directory so all content can be in a common place. Signed-off-by: Breno Lima <breno.lima@nxp.com> 
Commit ad7061ed742e ("doc: Move device tree bindings documentation to
 doc/device-tree-bindings") moved all device tree binding documentation
to doc/device-tree-bindings directory.

The current U-Boot project still have two documentation directories:

- doc/
- Documentation/

Move all documentation and sphinx files to doc directory so all content
can be in a common place.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
doc: binding: rename directory ram to memory-controller 2019-02-28T19:21:46+00:00 Patrick Delaunay patrick.delaunay@st.com 2019-02-26T12:09:00+00:00 3a29afcbbfd8eb6d58f06b1717807c036971ca58 Alignment with kernel directory name as it have already bindings for DDR controllers in the directory: Documentation/devicetree/bindings/memory-controller PS: the drivers using RAM u-class should be associated with this binding directory Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> 
Alignment with kernel directory name as it have already bindings for
DDR controllers in the directory:
Documentation/devicetree/bindings/memory-controller

PS: the drivers using RAM u-class should be associated with
    this binding directory

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
ram: Introduce K3 AM654 DDR Sub System driver 2018-11-16T21:51:58+00:00 Lokesh Vutla lokeshvutla@ti.com 2018-11-02T14:21:02+00:00 06bda1259ffc3ef899de70c7fb86b0982a2912f0 K3 based AM654 devices has DDR memory subsystem that comprises Synopys DDR controller, Synopsis DDR phy and wrapper logic to intergrate these blocks into the device. This DDR subsystem provides an interface to external SDRAM devices. Adding support for the initialization of the external SDRAM devices by configuring the DDRSS registers and using the buitin PHY routines. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com> 
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
ram: stm32mp1: add driver 2018-03-19T20:14:21+00:00 Patrick Delaunay patrick.delaunay@st.com 2018-03-12T09:46:11+00:00 e70f70aa6504bd6387c0a6d117e48383c5048b6b Add driver and binding for stm32mp1 ddr controller and phy Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> 
Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
ram: stm32: add second SDRAM bank management 2017-07-26T15:29:15+00:00 Patrice Chotard patrice.chotard@st.com 2017-07-18T15:37:27+00:00 f303aaf21b968ab959edcc354892f9eca8907e0b FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank. Even if only bank2 is used, some bank1 registers must be configured. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
ARM: DT: stm32f7: add sdram pin contol node 2017-05-08T15:39:03+00:00 Vikas Manocha vikas.manocha@st.com 2017-04-10T22:02:53+00:00 fd198ee1a8c5de79d31df9ca3c04d6d783868690 Also added DT binding doc for stm32 fmc(flexible memory controller). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> 
Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>