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<title>u-boot.git/doc/device-tree-bindings/ram, branch v2019.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2018-11-16T21:51:58Z</updated>
<entry>
<title>ram: Introduce K3 AM654 DDR Sub System driver</title>
<updated>2018-11-16T21:51:58Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2018-11-02T14:21:02Z</published>
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<id>urn:sha1:06bda1259ffc3ef899de70c7fb86b0982a2912f0</id>
<content type='text'>
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Signed-off-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Signed-off-by: Schuyler Patton &lt;spatton@ti.com&gt;
Signed-off-by: James Doublesin &lt;doublesin@ti.com&gt;
</content>
</entry>
<entry>
<title>ram: stm32mp1: add driver</title>
<updated>2018-03-19T20:14:21Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-03-12T09:46:11Z</published>
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<id>urn:sha1:e70f70aa6504bd6387c0a6d117e48383c5048b6b</id>
<content type='text'>
Add driver and binding for stm32mp1 ddr controller and phy

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>ram: stm32: add second SDRAM bank management</title>
<updated>2017-07-26T15:29:15Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-07-18T15:37:27Z</published>
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<id>urn:sha1:f303aaf21b968ab959edcc354892f9eca8907e0b</id>
<content type='text'>
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.

Even if only bank2 is used, some bank1 registers must be
configured.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ARM: DT: stm32f7: add sdram pin contol node</title>
<updated>2017-05-08T15:39:03Z</updated>
<author>
<name>Vikas Manocha</name>
<email>vikas.manocha@st.com</email>
</author>
<published>2017-04-10T22:02:53Z</published>
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<content type='text'>
Also added DT binding doc for stm32 fmc(flexible memory controller).

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
cc: Christophe KERELLO &lt;christophe.kerello@st.com&gt;
</content>
</entry>
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