Add i2c driver which can be used on both STM32F7 and STM32H7. This I2C block supports the following features: _ Slave and master modes _ Multimaster capability _ Standard-mode (up to 100 kHz) _ Fast-mode (up to 400 kHz) _ Fast-mode Plus (up to 1 MHz) _ 7-bit and 10-bit addressing mode _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) _ All 7-bit addresses acknowledge mode _ General call _ Programmable setup and hold times _ Easy to use event management _ Optional clock stretching _ Software reset Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
FMC is able to manage 2 SDRAM banks, but the current driver implementation is only able to manage the first SDRAM bank. Even if only bank2 is used, some bank1 registers must be configured. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros for these options and change the property from a boolean type to an integer type, and change their names to explicitly indicate what the property is really for. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Introduce various meaningful macros for FSP settings and switch over to use them instead of magic numbers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
"serial-debug-port-address" and "serial-debug-port-type" settings are actually reserved in the FSP UPD data structure. Remove them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Adding documentation on the new config properties:
'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
'u-boot,mmc-env-offset-redundant'
- overrides CONFIG_ENV_OFFSET_REDUND
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This adds documentation on the u-boot,spl-payload-offset property (which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in the SPL stage, if present). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
This adds a new firefly-rk3399 board, MIPI support for rk3399 and rk3288, rk818 pmic support, mkimage improvements for rockchip and a few other things.
This is a copy from kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>