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<title>u-boot.git/doc/device-tree-bindings, branch v2018.09-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/doc/device-tree-bindings?h=v2018.09-rc1</id>
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<updated>2018-07-24T13:25:23Z</updated>
<entry>
<title>doc: Move device tree bindings documentation to doc/device-tree-bindings</title>
<updated>2018-07-24T13:25:23Z</updated>
<author>
<name>Breno Lima</name>
<email>breno.lima@nxp.com</email>
</author>
<published>2018-07-21T00:48:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ad7061ed742e1312289644268859a0f4b512aaee'/>
<id>urn:sha1:ad7061ed742e1312289644268859a0f4b512aaee</id>
<content type='text'>
Currently the U-Boot project contains 2 documentation directories:

- doc/
- Documentation/

The Documentation directory only contains device tree bindings related
content, so move the 3 files to doc/device-tree-bindings/.

Signed-off-by: Breno Lima &lt;breno.lima@nxp.com&gt;
</content>
</entry>
<entry>
<title>spl: document 'chosen/u-boot, spl-boot-device'</title>
<updated>2018-07-20T23:55:26Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2018-05-24T15:15:51Z</published>
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<id>urn:sha1:2aa4abc1bd516ac8d741160bbed082761c8dc163</id>
<content type='text'>
To let the full U-Boot know where it was booted from (i.e. which of
the entries in /chosen/u-boot,spl-boot-order' contained a valid
image), we define (and document) /chosen/u-boot,spl-boot-device as the
property that could/should automatically be injected by SPL.

This commit only contains a documentation change, which documents the
new property and the intended usage.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: Klaus Goger &lt;klaus.goger@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: clk: support digital bypass</title>
<updated>2018-07-20T19:55:07Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-07-16T08:41:46Z</published>
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<id>urn:sha1:d219415544f099c5e553a556dc277377b9dbf64f</id>
<content type='text'>
HSE and LSE bypass shall support both analog and digital signals.
This patch add a way to select digital bypas case in the device tree
and set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN register
during clock tree initialization.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>fdt: Add device tree memory bindings</title>
<updated>2018-07-09T15:11:00Z</updated>
<author>
<name>Michael Pratt</name>
<email>mpratt@chromium.org</email>
</author>
<published>2018-06-11T19:07:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=90c08fa038451d6d7b7d8711bfd829b61d64c490'/>
<id>urn:sha1:90c08fa038451d6d7b7d8711bfd829b61d64c490</id>
<content type='text'>
Support a default memory bank, specified in reg, as well as
board-specific memory banks in subtree board-id nodes.

This allows memory information to be provided in the device tree,
rather than hard-coded in, which will make it simpler to handle
similar devices with different memory banks, as the board-id values
or masks can be used to match devices.

Signed-off-by: Michael Pratt &lt;mpratt@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Vadim Bendebury &lt;vbendeb@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: irq: Support discrete PIRQ routing registers via device tree</title>
<updated>2018-06-13T01:50:57Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-06-12T08:26:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=51050ff0a239f2640467d4c2fe54e0e8679a4093'/>
<id>urn:sha1:51050ff0a239f2640467d4c2fe54e0e8679a4093</id>
<content type='text'>
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume
consecutive PIRQ routing control registers. But this is not always
the case on some platforms. Introduce a new device tree property
intel,pirq-regmap to describe how the PIRQ routing register offset
is mapped to the link number and adjust the irq router driver to
utilize the mapping.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-sunxi</title>
<updated>2018-06-04T12:55:00Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-06-04T12:55:00Z</published>
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<id>urn:sha1:809e0e398a91db7bf8b4d6259d9bfc6fbd6bce83</id>
<content type='text'>
</content>
</entry>
<entry>
<title>mvebu: pinctrl: sync compatible string with Linux 4.17-rc4</title>
<updated>2018-05-29T06:33:05Z</updated>
<author>
<name>Evan Wang</name>
<email>xswang@marvell.com</email>
</author>
<published>2018-05-25T06:20:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f246648d3708c068c66409b36ddbccef7d7b0a48'/>
<id>urn:sha1:f246648d3708c068c66409b36ddbccef7d7b0a48</id>
<content type='text'>
For pinctrl driver of mvebu, the compatible strings
supported are defined differently from Linux version.
The patch aligned the compatible string with
Linux 4.17-rc4.

Signed-off-by: Evan Wang &lt;xswang@marvell.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>device-tree-bindings: phy: Sync sun4i-usb-phy bindings</title>
<updated>2018-05-28T11:10:43Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2018-05-09T06:05:51Z</published>
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<id>urn:sha1:85187b8073784803a05e24a06d0b4a709847848e</id>
<content type='text'>
Sync sun4i-usb-phy bindings from Linux, since the
drivers/phy/allwinner/phy-sun4i-usb.c follow similar.

Sync changes from Linux with below commit:
"phy: sun4i-usb: add support for R40 USB PHY"
(sha1: f3d96f8d23d8e6d0b7642ee946b9b2ac3418fb4d)

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Acked-by: Jun Nie &lt;jun.nie@linaro.org&gt;
</content>
</entry>
<entry>
<title>doc: device-tree-bindings: add Sandbox TPMv2.0 module info</title>
<updated>2018-05-26T00:13:00Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2018-05-15T09:57:26Z</published>
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<id>urn:sha1:31b106fc1c91e2a339523f6e703825512b4d23b9</id>
<content type='text'>
Add Sandbox TPMv2.0 module bindings.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>doc: device-tree-bindings: add TIS TPMv2.0 SPI module info</title>
<updated>2018-05-26T00:12:59Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2018-05-15T09:57:23Z</published>
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<id>urn:sha1:8ee59472cb83cb7d5d28c6e1737a3e8a7ffb7cc3</id>
<content type='text'>
Add TIS TPMv2.0 SPI module bindings.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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