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<title>u-boot.git/doc/device-tree-bindings, branch v2021.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/doc/device-tree-bindings?h=v2021.10</id>
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<updated>2021-09-11T09:02:02Z</updated>
<entry>
<title>doc: Complete the list of available runtime-config options</title>
<updated>2021-09-11T09:02:02Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-09-09T20:10:32Z</published>
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<id>urn:sha1:19e699fb2b7357f2f71ac928499cbb4442f5d576</id>
<content type='text'>
The current list is missing a few items. Add them.

Reviewed-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>doc: Tidy up the bindings for the config/ node</title>
<updated>2021-09-11T09:02:02Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-09-09T20:10:31Z</published>
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<id>urn:sha1:8eb4a76d85d3b337f65132022b518e5798aa2472</id>
<content type='text'>
Sort these and add a type so it is clear how to set the value. Add a note
about usage to the top. Correct the 'no-keyboard' binding which is missing
a prefix.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>bootcount: add a new driver with syscon as backend</title>
<updated>2021-08-22T09:04:52Z</updated>
<author>
<name>Nandor Han</name>
<email>nandor.han@vaisala.com</email>
</author>
<published>2021-06-10T12:40:38Z</published>
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<id>urn:sha1:c50b21b70523939c561d0455a2c423f63a9162ca</id>
<content type='text'>
The driver will use a syscon regmap as backend and supports both
16 and 32 size value. The value will be stored in the CPU's endianness.

Signed-off-by: Nandor Han &lt;nandor.han@vaisala.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>doc: stm32mp1: add page for device tree bindings</title>
<updated>2021-08-14T18:54:41Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@foss.st.com</email>
</author>
<published>2021-08-02T16:08:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=551a959a8c11e7f3452e0c2f24db85dffebc1e91'/>
<id>urn:sha1:551a959a8c11e7f3452e0c2f24db85dffebc1e91</id>
<content type='text'>
With device tree binding migration to yaml it is difficult to synchronize
the binding from Linux kernel to U-Boot.

Instead of maintaining the same dt bindings, this patch adds in the U-Boot
documentation the path to the device tree bindings in Linux kernel for
STMicroelectronics devices, when they are used without modification.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;

Add links for referenced text files.
Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>arm64: a37xx: pinctrl: Correct PWM pins definitions</title>
<updated>2021-07-31T07:59:58Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2021-07-23T17:57:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5534fb4f4833eda4e1a2df1c89a75db72e5e2008'/>
<id>urn:sha1:5534fb4f4833eda4e1a2df1c89a75db72e5e2008</id>
<content type='text'>
The PWM pins on North Bridge on Armada 37xx can be configured into PWM
or GPIO functions. When in PWM function, each pin can also be configured
to drive low on 0 and tri-state on 1 (LED mode).

The current definitions handle this by declaring two pin groups for each
pin:
- group "pwmN" with functions "pwm" and "gpio"
- group "ledN_od" ("od" for open drain) with functions "led" and "gpio"

This is semantically incorrect. The correct definition for each pin
should be one group with three functions: "pwm", "led" and "gpio".

Change the "pwmN" groups to support "led" function.

Remove "ledN_od" groups. This cannot break backwards compatibility with
older device trees: no device tree uses it since there is no PWM driver
for this SOC yet. Also "ledN_od" groups are not even documented.

Signed-off-by: Marek Behún &lt;marek.behun@nic.cz&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>reboot-mode: read the boot mode from RTC memory</title>
<updated>2021-07-23T14:16:39Z</updated>
<author>
<name>Nandor Han</name>
<email>nandor.han@vaisala.com</email>
</author>
<published>2021-06-10T13:56:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c74675bd904b6ce9d5820a80f27793c0583fd54c'/>
<id>urn:sha1:c74675bd904b6ce9d5820a80f27793c0583fd54c</id>
<content type='text'>
RTC devices could provide battery-backed memory that can be used for
storing the reboot mode magic value.

Add a new reboot-mode back-end that uses RTC to store the reboot-mode
magic value. The driver also supports both endianness modes.

Signed-off-by: Nandor Han &lt;nandor.han@vaisala.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>reboot-mode: read the boot mode from GPIOs status</title>
<updated>2021-07-23T14:16:39Z</updated>
<author>
<name>Nandor Han</name>
<email>nandor.han@vaisala.com</email>
</author>
<published>2021-06-10T13:56:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f9db2f16cb6fc7b6d05b0e70de65881bc97ba5c2'/>
<id>urn:sha1:f9db2f16cb6fc7b6d05b0e70de65881bc97ba5c2</id>
<content type='text'>
A use case for controlling the boot mode is when the user wants
to control the device boot by pushing a button without needing to
go in user-space.

Add a new backed for reboot mode where GPIOs are used to control the
reboot-mode. The driver is able to scan a predefined list of GPIOs
and return the magic value. Having the modes associated with
the magic value generated based on the GPIO values, allows the
reboot mode uclass to select the proper mode.

Signed-off-by: Nandor Han &lt;nandor.han@vaisala.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: pci: Allow binding of some devices before relocation</title>
<updated>2021-07-15T11:49:50Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-06-27T23:50:57Z</published>
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<id>urn:sha1:f5cbb5c7cd24b5e674933bb381d854c02512d2d9</id>
<content type='text'>
At present only bridge devices are bound before relocation, to save space
in pre-relocation memory. In some cases we do actually want to bind a
device, e.g. because it provides the console UART. Add a devicetree
binding to support this.

Use the PCI_VENDEV() macro to encode the cell value. This is present in
U-Boot but not used, so move it to the binding header-file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>firmware: ti_sci: Add support for Resoure Management at R5 SPL stage.</title>
<updated>2021-06-11T13:48:52Z</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2021-06-07T14:17:49Z</published>
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<id>urn:sha1:5d5a699855a704646b10c4f04dc9ce0650ceace3</id>
<content type='text'>
On J721e and J7200, MCU R5 core (boot master) itself would run Device
Manager (DM) Firmware and interact with TI Foundational Security (TIFS)
firmware to enable DMA and such other Resource Management (RM) services.
So, during R5 SPL stage there is no such RM service available and ti_sci
driver will have to directly interact with TIFS using DM to DMSC
channels to request RM resources.

Therefore add DT binding and driver for the same. This driver will
handle Resource Management services at R5 SPL stage.

Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Link: https://lore.kernel.org/r/20210607141753.28796-4-vigneshr@ti.com
</content>
</entry>
<entry>
<title>dt-bindings: memory-controller: Add K3 AM64 DDRSS compatible</title>
<updated>2021-05-12T11:00:52Z</updated>
<author>
<name>Dave Gerlach</name>
<email>d-gerlach@ti.com</email>
</author>
<published>2021-05-11T15:21:59Z</published>
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<id>urn:sha1:760b7488f531a627ce6ed0a1bddc7a8522fbf612</id>
<content type='text'>
Update the k3-ddrss DT binding document to include compatible
for k3,am64-ddrss.

Signed-off-by: Dave Gerlach &lt;d-gerlach@ti.com&gt;
</content>
</entry>
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