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<title>u-boot.git/doc, branch v2013.01-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/doc?h=v2013.01-rc1</id>
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<updated>2012-11-02T22:13:29Z</updated>
<entry>
<title>git-mailrc: Change x86 maintainer to Simon</title>
<updated>2012-11-02T22:13:29Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2012-10-31T12:41:49Z</published>
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<id>urn:sha1:b4a2e43570f335cf91b8cbeb8f74c49701217c1b</id>
<content type='text'>
Grame is still listed since he has agreed to continue with some review.
Also add an alias to shorten things.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>fs: separate CONFIG_FS_{FAT, EXT4} from CONFIG_CMD_{FAT, EXT*}</title>
<updated>2012-10-29T21:21:19Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2012-10-22T06:43:50Z</published>
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<id>urn:sha1:03e2ecf6b83e43803f7eed9547d0973b7eb1c8fc</id>
<content type='text'>
This makes the FAT and ext4 filesystem implementations build if
CONFIG_FS_{FAT,EXT4} are defined, rather than basing the build on
whether CONFIG_CMD_{FAT,EXT*} are defined. This will allow the
filesystems to be built separately from the filesystem-specific commands
that use them. This paves the way for the creation of filesystem-generic
commands that used the filesystems, without requiring the filesystem-
specific commands.

Minor documentation changes are made for this change.

The new config options are automatically selected by the old config
options to retain backwards-compatibility.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Benoît Thébaudeau &lt;benoit.thebaudeau@advansee.com&gt;
</content>
</entry>
<entry>
<title>PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)</title>
<updated>2012-10-28T19:17:25Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2012-10-24T02:36:15Z</published>
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<id>urn:sha1:1b0757eceddf037aad99ab59217a3a5c215e15d1</id>
<content type='text'>
These boards have long reached EOL, and there has been no indication
of any active users of such hardware for years.  Get rid of the dead
weight.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Wolfgang Grandegger &lt;wg@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: arm925t: remove SX1 board</title>
<updated>2012-10-26T21:22:01Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2012-10-18T10:15:45Z</published>
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<id>urn:sha1:53c41548a9fd7f0595c81c47e1ac3d9671d753e4</id>
<content type='text'>
SX1 does not build properly by itself, is not built
as part of MAKEALL arm or MAKEALL -a arm, and is only
present in Makefile, not boards.cfg. As it also has no
entry in MAINTAINERS, it is orphan and non-functional.
Remove it.

Signed-off-by: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
</content>
</entry>
<entry>
<title>arm: Remove support for lpc2292</title>
<updated>2012-10-26T20:35:20Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2012-10-03T08:54:08Z</published>
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<id>urn:sha1:6f62f4207112013852be87dc2b9c7c570eba11c9</id>
<content type='text'>
This stuff has been rotting in the tree for a year now. Remove it.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>ColdFire: Add Freescale MCF54418TWR ColdFire development board support</title>
<updated>2012-10-24T14:27:46Z</updated>
<author>
<name>Alison Wang</name>
<email>b18965@freescale.com</email>
</author>
<published>2012-10-18T19:25:52Z</published>
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<id>urn:sha1:186fc4db263fc6332d6712be99a9a387087d29c7</id>
<content type='text'>
Add Freescale MCF54418TWR ColdFire development board support.

Signed-off-by: TsiChung Liew &lt;tsicliew@gmail.com&gt;
Signed-off-by: Jason Jin &lt;Jason.jin@freescale.com&gt;
Signed-off-by: Alison Wang &lt;b18965@freescale.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx</title>
<updated>2012-10-22T23:54:38Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2012-10-22T23:54:38Z</published>
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<id>urn:sha1:c7656bab411433f987baa2288eff8c78ddc0f378</id>
<content type='text'>
</content>
</entry>
<entry>
<title>powerpc/t4qds: Add T4QDS board</title>
<updated>2012-10-22T20:52:46Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2012-10-11T07:13:37Z</published>
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<id>urn:sha1:ee52b188ca2c631427d197056ab7b71b9e23bde7</id>
<content type='text'>
The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.

SERDES Connections
  32 lanes grouped into four 8-lane banks
  Two “front side” banks dedicated to Ethernet
  Two “back side” banks dedicated to other protocols
DDR Controllers
  Three independant 64-bit DDR3 controllers
  Supports rates up to 2133 MHz data-rate
  Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA

Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.

Detail information can be found in doc/README.t4qds

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1</title>
<updated>2012-10-22T19:31:32Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2012-10-08T07:44:30Z</published>
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<id>urn:sha1:ffd06e0231ac3fd0c5810f39f6e23527948df1c7</id>
<content type='text'>
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc8xxx: Add auto select bank interleaving mode</title>
<updated>2012-10-22T19:31:30Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2012-10-08T07:44:27Z</published>
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<id>urn:sha1:89b78095681fd3dfd359082ba62d80551a114ab0</id>
<content type='text'>
Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.

Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
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