u-boot.git/doc, branch v2014.01-rc3 Unnamed repository; edit this file 'description' to name the repository. doc: SPI: Update status.txt 2014-01-12T16:10:23+00:00 Jagannadha Sutradharudu Teki jaganna@xilinx.com 2014-01-08T17:34:44+00:00 736ce857da3ecaa375130beede6a18000251ada8 Updated current SPI subsyetem status. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
Updated current SPI subsyetem status.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Add dual memories support - DUAL_PARALLEL 2014-01-12T16:10:22+00:00 Jagannadha Sutradharudu Teki jaganna@xilinx.com 2014-01-06T18:41:35+00:00 056fbc73d54df64adcb93c513cba708acb2683bd This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.

For more info - see doc/SPI/README.dual-flash

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
sf: Add dual memories support - DUAL_STACKED 2014-01-12T16:10:11+00:00 Jagannadha Sutradharudu Teki jaganna@xilinx.com 2014-01-12T16:10:11+00:00 f77f469117ab3184ac45683a50dc446265be28cc This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.

For more info - see doc/SPI/README.dual-flash

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
spi: Add Faraday SPI controller support 2014-01-11T06:51:30+00:00 Kuo-Jung Su dantesu@faraday-tech.com 2013-12-20T07:24:30+00:00 66cb9eb1d6372b0d39b793688f80db5834d3ffab The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> CC: Tom Rini <trini@ti.com> 
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.

NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
CC: Tom Rini <trini@ti.com>
Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-01-10T15:56:00+00:00 Tom Rini trini@ti.com 2014-01-10T15:56:00+00:00 7f673c99c2d8d1aa21996c5b914f06d784b080ca Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com> 
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
doc: Update the zynq u-boot status 2014-01-10T14:18:33+00:00 Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com 2014-01-08T20:18:31+00:00 10a147bc665367111920be657409a5d56d3c0590 Updated doc/README.zynq to current status Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
Updated doc/README.zynq to current status

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
zynq: Add support to find bootmode 2014-01-10T14:18:33+00:00 Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com 2014-01-08T20:18:21+00:00 b3de92495f23db58a2643fb9328edacbf9a17f1c Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.

Added this functionality on board_late_init as it's not
needed for normal initializtion part.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
doc: zynq: Add information on zynq u-boot 2014-01-10T14:18:32+00:00 Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com 2014-01-08T20:18:11+00:00 ba45a072bf9a186d99aae35af56699eeb7704b1c Information on zynq u-boot about - zynq boards - mainline status - TODO Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 
Information on zynq u-boot about
- zynq boards
- mainline status
- TODO

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
arm64: core support 2014-01-09T15:08:44+00:00 David Feng fenghua@phytium.com.cn 2013-12-14T03:47:35+00:00 0ae7653128c80a4f2920cbe9b124792c2fd9d9e0 Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> 
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: David Feng <fenghua@phytium.com.cn>
socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA 2014-01-09T09:53:55+00:00 Chin Liang See clsee@altera.com 2013-12-31T00:26:14+00:00 c5c1af21764d9423b45c1d03e835c4547a8bc5cb To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> 
To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>