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<title>u-boot.git/doc, branch v2017.11-rc1</title>
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<id>http://cgit.235523.xyz/u-boot.git/atom/doc?h=v2017.11-rc1</id>
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<updated>2017-09-30T22:33:34Z</updated>
<entry>
<title>rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-order</title>
<updated>2017-09-30T22:33:34Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-09-29T17:27:57Z</published>
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<id>urn:sha1:80e9f88e67398ae65c89af3bace59e7e14debd33</id>
<content type='text'>
It is often desirable to configure the spl-boot-order (i.e. the order
that SPL probes devices to find the FIT image containing a full U-Boot)
such that it contains 'the same device the SPL stage was booted from'
early on.  To support this, we introduce the 'same-as-spl' specifier
for the spl-boot-order property.

This commit adds:
 - documentation for the new board_spl_was_booted_from() function that
   individual SoCs/boards should provide, if they can determine where
   the SPL was booted from
 - implements the new board_spl_was_booted_from() stub function
 - adds support for handling the 'same-as-spl' specifier and calling
   into the per-SoC/per-board support code.

This also updates the documentation for the 'u-boot,spl-boot-order'
property.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rk3288: vyasa: Add TPL support</title>
<updated>2017-09-30T22:33:33Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2017-09-27T17:33:12Z</published>
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<id>urn:sha1:532cb7f5ada0cc3779c33606d760ec99f6aa847a</id>
<content type='text'>
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.

So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>dm: reset: add stm32 reset driver</title>
<updated>2017-09-22T11:40:01Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-09-13T16:00:07Z</published>
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<id>urn:sha1:23a06416858d839ee62dc00562be956be6d84bd2</id>
<content type='text'>
This driver is adapted from linux drivers/reset/reset-stm32.c
It's compatible with STM32 F4/F7/H7 SoCs.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

To add support for each SoC family, a SoC's specific
include/dt-binfings/mfd/stm32xx-rcc.h file must be added.

This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
Other SoCs support will be added in the future.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: clk: add clk driver support for stm32h7 SoCs</title>
<updated>2017-09-22T11:40:01Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-09-13T16:00:06Z</published>
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<id>urn:sha1:4c3aebd56a035740f04fce44ce6c398afbb5ad86</id>
<content type='text'>
This driver implements basic clock setup, only clock gating
is implemented.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].

[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: Add dwc3 glue driver support for STi</title>
<updated>2017-09-22T11:39:59Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-09-05T09:04:24Z</published>
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<id>urn:sha1:40d1a31e6329da8feecc555f2bdfb8da463bdd40</id>
<content type='text'>
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.

Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>usb: phy: Add STi USB2 PHY</title>
<updated>2017-09-22T11:39:57Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-09-05T09:04:21Z</published>
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<id>urn:sha1:b7ca56dcda8a2be0e7ca6142448ab4153926aafc</id>
<content type='text'>
This is the generic phy driver for the picoPHY ports
used by USB2/1.1 controllers. It is found on STiH407 SoC
family from STMicroelectronics.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-uniphier</title>
<updated>2017-09-18T14:58:10Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-09-18T14:58:10Z</published>
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<id>urn:sha1:45d19acb2f340a3a8092cedcdef01d3e9efb8342</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: uniphier: merge two defconfig files into uniphier_v7_defconfig</title>
<updated>2017-09-18T11:26:06Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-09-15T12:43:20Z</published>
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<id>urn:sha1:81b9bb5fcb5e8d42a7ccfeaf5afed9ff77014761</id>
<content type='text'>
The main difference between Pro4 and PXs2/LD6b is the Denali NAND
IP version.  This is now distinguished by DT.  Merge the two defconfig
files into uniphier_v7_defconfig.

Update the README.uniphier too.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-x86</title>
<updated>2017-09-17T15:46:51Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-09-17T15:46:51Z</published>
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<id>urn:sha1:c07f38208a73bbe3efaa939d6742096c1cb7e0ce</id>
<content type='text'>
</content>
</entry>
<entry>
<title>x86: Support Intel Cherry Hill board</title>
<updated>2017-09-16T06:57:44Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-08-16T05:42:02Z</published>
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<id>urn:sha1:eb45787b396f197f2d4c3bc3556c48421528f62b</id>
<content type='text'>
This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:

- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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