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<title>u-boot.git/doc, branch v2018.01-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>rockchip: rk3399-puma: add code to allow forcing a power-on reset</title>
<updated>2017-11-30T21:59:54+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-11-28T16:56:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ae0d33a7291a164a11ae034bcf4f71226b2bef48'/>
<id>ae0d33a7291a164a11ae034bcf4f71226b2bef48</id>
<content type='text'>
The reset circuitry in the RK3399 only resets 'almost all logic' when
a software reset is performed.  To make our software maintenance
easier in the future, we want to have the option (controlled by a DTS
property) to force all reset causes other than a power-on reset to
trigger a power-on reset via a GPIO trigger.

This adds the necessary support to the rk3399-puma (i.e. RK3399-Q7)
board-support and the documentation for the new property
(sysreset-gpio) within the /config-node.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: Klaus Goger &lt;klaus.goger@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
The reset circuitry in the RK3399 only resets 'almost all logic' when
a software reset is performed.  To make our software maintenance
easier in the future, we want to have the option (controlled by a DTS
property) to force all reset causes other than a power-on reset to
trigger a power-on reset via a GPIO trigger.

This adds the necessary support to the rk3399-puma (i.e. RK3399-Q7)
board-support and the documentation for the new property
(sysreset-gpio) within the /config-node.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: Klaus Goger &lt;klaus.goger@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: spi: Add andestech atcspi200 spi binding doc</title>
<updated>2017-11-30T01:45:29+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2017-11-15T08:03:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=872cd42e706983b2efa928ec038f1f80d5eb5e87'/>
<id>872cd42e706983b2efa928ec038f1f80d5eb5e87</id>
<content type='text'>
Add a document to describe Andestech atcspi200 spi and
binding information.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a document to describe Andestech atcspi200 spi and
binding information.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: timer: Add andestech atcpit100 timer</title>
<updated>2017-11-30T01:39:12+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rickchen36@gmail.com</email>
</author>
<published>2017-11-23T02:22:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=410d129e8c68b994dee69c89dd8e52931458ff85'/>
<id>410d129e8c68b994dee69c89dd8e52931458ff85</id>
<content type='text'>
Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: rick &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: rick &lt;rick@andestech.com&gt;
Signed-off-by: Rick Chen &lt;rickchen36@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-socfpga</title>
<updated>2017-11-28T14:30:36+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-11-28T14:30:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=65972a0b6204aa298b70b7ebd755bb1ce1ed53ee'/>
<id>65972a0b6204aa298b70b7ebd755bb1ce1ed53ee</id>
<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>ARM: socfpga: add bindings doc for arria10 fpga manager</title>
<updated>2017-11-26T01:34:10+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2017-09-25T08:39:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=772f8765d71a1929111288a2ed9b5577740b1538'/>
<id>772f8765d71a1929111288a2ed9b5577740b1538</id>
<content type='text'>
This DT binding doc is porting from Linux DT binding doc.
commit 1adcbea4201a6852362aa5ece573f1f169b28113

Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.

Signed-off-by: Alan Tull &lt;atull@opensource.altera.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-By: Moritz Fischer &lt;moritz.fischer@ettus.com&gt;
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This DT binding doc is porting from Linux DT binding doc.
commit 1adcbea4201a6852362aa5ece573f1f169b28113

Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.

Signed-off-by: Alan Tull &lt;atull@opensource.altera.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-By: Moritz Fischer &lt;moritz.fischer@ettus.com&gt;
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MAINTAINERS: Update maintainer for USB xHCI</title>
<updated>2017-11-26T01:22:36+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-11-06T15:39:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c0c5f910adbe703aa3d353fbf2c63e9ebc779943'/>
<id>c0c5f910adbe703aa3d353fbf2c63e9ebc779943</id>
<content type='text'>
As discussed with Marek, this adds myself as the maintainer to
offload the USB xHCI part.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
As discussed with Marek, this adds myself as the maintainer to
offload the USB xHCI part.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: rk3188: use boot0 hook to load up SPL in 2 steps</title>
<updated>2017-11-21T22:57:22+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-10-10T14:21:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4d9253fb76f59c6f474ca54fe2d45c5706cd86e3'/>
<id>4d9253fb76f59c6f474ca54fe2d45c5706cd86e3</id>
<content type='text'>
For the RK3188, the BROM will attempt to load up the first stage
image (SPL for the RK3188) in two steps: first 1KB to offset 0x800
in the SRAM and then the remainder to offset 0xc00 in the SRAM.
It always enters at 0x804, though.

With this changeset, the RK3188 boot removes the TPL (stub) stage and
builds a single SPL binary that utilizes the early back-to-bootrom via
the boot0-hook.

Consequently, the passing of the saved boot params via pmu-&gt;os_reg[2]
is also removed.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For the RK3188, the BROM will attempt to load up the first stage
image (SPL for the RK3188) in two steps: first 1KB to offset 0x800
in the SRAM and then the remainder to offset 0xc00 in the SRAM.
It always enters at 0x804, though.

With this changeset, the RK3188 boot removes the TPL (stub) stage and
builds a single SPL binary that utilizes the early back-to-bootrom via
the boot0-hook.

Consequently, the passing of the saved boot params via pmu-&gt;os_reg[2]
is also removed.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>thermal: ti-bandgap: Add support for temperature sensor</title>
<updated>2017-11-21T13:03:38+00:00</updated>
<author>
<name>Faiz Abbas</name>
<email>faiz_abbas@ti.com</email>
</author>
<published>2017-11-14T10:42:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8502f9f6d7781b5f461d7e3f7c958a45f64fdfa1'/>
<id>8502f9f6d7781b5f461d7e3f7c958a45f64fdfa1</id>
<content type='text'>
The dra7xx series of SOCs contain a temperature sensor and an
associated analog-to-digital converter (ADC) which produces
an output which is proportional to the SOC temperature.
Add support for this temperature sensor.

Signed-off-by: Faiz Abbas &lt;faiz_abbas@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The dra7xx series of SOCs contain a temperature sensor and an
associated analog-to-digital converter (ADC) which produces
an output which is proportional to the SOC temperature.
Add support for this temperature sensor.

Signed-off-by: Faiz Abbas &lt;faiz_abbas@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Makefile: add coccicheck target</title>
<updated>2017-11-21T01:18:38+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2017-11-19T13:33:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8a28caf02b7763f3d0b3813805ecd3ede0589c73'/>
<id>8a28caf02b7763f3d0b3813805ecd3ede0589c73</id>
<content type='text'>
Coccinelle is a program for static code analysis.
For details on Coccinelle see

	http://coccinelle.lip6.fr/

Add scripts/coccicheck copied from Linux kernel v4.14.

The coccicheck script executes the tests *.cocci in
directory scripts/coccinelle by calling spatch.

In Makefile add a coccicheck target. You can use it with

	make coccicheck MODE=&lt;mode&gt;

	where mode in patch, report, context, org.

Add a copy of Linux v4.14 file Documentation/dev-tools/coccinelle.rst
as doc/README.coccinelle.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Coccinelle is a program for static code analysis.
For details on Coccinelle see

	http://coccinelle.lip6.fr/

Add scripts/coccicheck copied from Linux kernel v4.14.

The coccicheck script executes the tests *.cocci in
directory scripts/coccinelle by calling spatch.

In Makefile add a coccicheck target. You can use it with

	make coccicheck MODE=&lt;mode&gt;

	where mode in patch, report, context, org.

Add a copy of Linux v4.14 file Documentation/dev-tools/coccinelle.rst
as doc/README.coccinelle.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>env: Save environment at the end of an MMC partition</title>
<updated>2017-11-17T12:44:13+00:00</updated>
<author>
<name>Jorge Ramirez-Ortiz</name>
<email>jorge.ramirez-ortiz@linaro.org</email>
</author>
<published>2017-11-06T13:16:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c9e87ba66540cf72c164674a71af43853d087ba8'/>
<id>c9e87ba66540cf72c164674a71af43853d087ba8</id>
<content type='text'>
Allow the platform to define a partition by name at the end of which
the environment data will be located.

Signed-off-by: Jorge Ramirez-Ortiz &lt;jorge.ramirez-ortiz@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allow the platform to define a partition by name at the end of which
the environment data will be located.

Signed-off-by: Jorge Ramirez-Ortiz &lt;jorge.ramirez-ortiz@linaro.org&gt;
</pre>
</div>
</content>
</entry>
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