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<title>u-boot.git/doc, branch v2019.07-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/doc?h=v2019.07-rc3</id>
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<updated>2019-05-24T12:13:27Z</updated>
<entry>
<title>Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-boot</title>
<updated>2019-05-24T12:13:27Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-24T12:13:27Z</published>
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<id>urn:sha1:866a78dc28411f4c76ba887f439f69f1116d8a6b</id>
<content type='text'>
- Add various STM32MP1 fixes for serial, env, clk, board, i2c ...

- Add STM32MP1 DDR driver update:
	These update introduce the DDR interactive mode described in:
	https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode

	This mode is used by the CubeMX: DDR tuning tool.
	https://wiki.st.com/stm32mpu/index.php/STM32CubeMX

	The DDR interactive mode is NOT activated by default because
	it increase the SPL size and slow down the boot time
	(200ms wait added).
</content>
</entry>
<entry>
<title>m68k: add basic set of devicetrees</title>
<updated>2019-05-24T03:14:38Z</updated>
<author>
<name>Angelo Dureghello</name>
<email>angelo@sysam.it</email>
</author>
<published>2019-03-13T20:46:41Z</published>
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<id>urn:sha1:b5867b1a7a4c45c6a5a6a97f866dd180631ebf2b</id>
<content type='text'>
This patch adds a basic group of devicetrees, one for each
cpu family, including actually just uart and dspi devices,
since these are the drivers supporting devicetree (support
added in this patch-set).

Acked-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Signed-off-by: Angelo Dureghello &lt;angelo@sysam.it&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: ram: update parameter array initialization</title>
<updated>2019-05-23T09:38:10Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-04-10T12:09:25Z</published>
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<id>urn:sha1:53bb8316583bf2206918457ec049b001d5b40a0f</id>
<content type='text'>
Force alignment of the size of parameters array with
the expected value in the binding, that allows compilation
error when the array size change.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: ram: change ddr speed to kHz</title>
<updated>2019-05-23T09:38:10Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-04-10T12:09:23Z</published>
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<id>urn:sha1:c60fed14f64ac82721ef9afc6ac47e0379538900</id>
<content type='text'>
Allow fractional support in DDR tools.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: update RCC binding after kernel realignment</title>
<updated>2019-05-23T09:36:46Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-04-18T15:32:41Z</published>
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<id>urn:sha1:3351768ef9297fa9af89d704effeb1ca1508905b</id>
<content type='text'>
RCC is no more a mfd and add a complete example
and alignment with latest TF-A binding

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>splash: Use splashfile instead of location-&gt;name</title>
<updated>2019-05-20T09:55:42Z</updated>
<author>
<name>Leo Ruan</name>
<email>tingquan.ruan@cn.bosch.com</email>
</author>
<published>2019-02-08T09:51:35Z</published>
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<id>urn:sha1:3d92f31762d8744e9b905b631dc267276adc50d4</id>
<content type='text'>
The splash image could be loaded from different sources (e.g. sf, mmc)
with different formats (e.g. raw, file-system). These sources are
structured by a board dependent object 'splash_location'. To decide
where is the splash image loaded, following environment variables are
used to select the splash source and file:
- 'splashsource' is used to select the splash source by setting its
  value to specified name of splash location.
- 'splashfile' specify the name of splash image file

But, when loads the splash image from FIT, the name of splash image
within FIT is specified by splash location name. Due to the splash
location name is already used for the splash source, its name may
conflicts with the name of splash image.

To solve the conflict, the environment variable 'splashfile' is used
to specify the splash image in FIT, and keeps the splash location
name for the splash source.

Signed-off-by: Leo Ruan &lt;tingquan.ruan@cn.bosch.com&gt;
Signed-off-by: Mark Jonas &lt;mark.jonas@de.bosch.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Tomas Melin &lt;tomas.melin@vaisala.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-socfpga</title>
<updated>2019-05-13T11:13:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-13T11:13:03Z</published>
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<id>urn:sha1:d2d8f73da4b648ad21b1afb481f0bcd035ebe029</id>
<content type='text'>
- A10 FPGA programming support, Gen5 livetree conversion
</content>
</entry>
<entry>
<title>ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10</title>
<updated>2019-05-10T20:48:10Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2019-05-07T09:42:24Z</published>
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<id>urn:sha1:5c2ae96b60ade14ea1f4afeb50e2a3de56493bcc</id>
<content type='text'>
This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>sh: sh3: Remove CPU support</title>
<updated>2019-05-10T20:43:18Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2019-05-07T20:04:05Z</published>
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<id>urn:sha1:d0487da83f916181eba57251ca28b2cb4d728092</id>
<content type='text'>
This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Chris Brandt &lt;chris.brandt@renesas.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
Cc: Vladimir Zapolskiy &lt;vz@mleia.com&gt;
Cc: Yoshihiro Shimoda &lt;shimoda.yoshihiro.uh@renesas.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchip</title>
<updated>2019-05-09T16:36:17Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-09T11:12:51Z</published>
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<id>urn:sha1:f30f268a07b0c9e4418366debc9ad0100a47cea4</id>
<content type='text'>
Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
</content>
</entry>
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